Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1994-08-05
2001-08-07
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000, C711S138000
Reexamination Certificate
active
06272595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of integrated circuit devices. More particularly, this invention relates to cache memory circuits.
2. Background
A cache memory is a random access memory that buffers data from a main memory. A cache memory is typically employed to provide high bandwidth memory accessing to a processor. Typically, such a cache memory reflects selected locations of the main memory. A typical prior cache memory contains a memory array that is usually organized into a set of cache blocks. The cache blocks are typically referred to as cache lines. A cache memory is usually smaller than the corresponding main memory. As a consequence, each cache line stored in the cache memory includes a corresponding address tag that identifies the main memory location for that cache line.
Prior cache memories typically implement a pipelined write architecture. In such a cache memory, a write operation requires two clock cycles. During a first cycle of the write operation, the processor transfers an address and a data value for the write operation to the cache memory. The cache memory typically latches the address and the data value into a set of pipeline registers. During a second cycle of the write operation, the cache memory transfers the data value and associated address tags into the memory array.
A prior pipelined write architecture for a cache memory typically provides high input bandwidth during write operations. Such an architecture enables the processor to supply a new write data value to the cache memory during each clock cycle while the cache memory transfers the previous write data value into the memory array.
Unfortunately, a pipelined write architecture typically causes a wait state in the cache memory for a read operation that immediately follows a write operation. Such a wait state usually occurs while the cache memory transfers the write data value of the preceding write operation into the memory array. A wait cycle is typically required because the read operation may be targeted for the same cache line as the preceding write operation that is buffered in the write pipeline registers. The cache memory must transfer the buffered write operation to the memory array before the subsequent read operation can be processed. Unfortunately, such wait cycles decrease the overall throughput to such a prior cache memory.
Other prior cache memories implement single cycle non-pipelined write operations. In this type of cache memory, the processor supplies the write data value to the cache memory early in the write cycle in order to enable the cache memory to transfer the write data value to the memory array during the same cycle. Unfortunately, single cycle cache memories stress the write timing of the processor. As a consequence, such prior single cycle cache memories are typically limited to lower input bandwidths than cache memories having a pipelined write architecture.
SUMMARY AND OBJECTS OF THE INVENTION
One object of the present invention is to enable high bandwidth read and write accesses to a cache memory.
Another object of the present invention is enable one cycle read and one cycle write operations from a processor to a cache memory.
Another object of the present invention is to provide a cache memory that does not impose a cache access wait state if a read operation immediately follows a write operation wherein the read and write operations target the same cache line.
A further object of the present invention is to relax the timing constraints for cache memory design by removing cache memory writes from the critical speed path to the cache memory array.
Another object of the present invention is to buffer a write operation to a cache memory and to perform the buffered write operation during a later cycle to the cache memory array with relaxed timing constraints.
Another object of the present invention is to access the buffered write operation and to merge the buffered data with cache array data for a read operation targeted for the same cache line as the buffered write operation.
Another object of the present invention is to merge the buffered data with cache array data for a read operation without causing delays in the critical speed path for the read operation.
These and other objects of the invention are provided by a cache memory circuit comprising a memory array for buffering a set of cache lines and a set of corresponding address tags. The cache memory circuit includes a store hit buffer coupled to receive and store a write operation to the cache memory circuit. The store hit buffer comprises circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer. The cache memory circuit further comprises circuitry for merging the write operation from the store hit buffer with the read operation.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.
REFERENCES:
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5517660 (1996-05-01), Rosich
“Computer Architecture A Qualitative Approach”; Patterson, David et al.; Morgan Kaufman Publishers, San Mateo Ca; 1990; pp. 409-417, 1990.*
Patterson et al.,Computer Architecture A Qualitative Approach, 1990, pp. 408-417.
Doweck Jack
Rosen Eitan
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Matthew
Tran Denise
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