N-sided polygonal cell layout for multiple cell transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257356, 257357, 257358, 257401, 257350, 257351, 257368, 257369, H01L 21335

Patent

active

058523154

ABSTRACT:
A MOS transistor cell is disclosed for a multiple cell MOS transistor, such as in an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n.gtoreq.8. A drain region is provided in a substrate which occupies an area with n-sided polygonal shaped boundaries. Surrounding the drain, is a channel region which occupies an n-sided polygonal shaped area. Surrounding the channel region is a source region provided in the substrate which occupies an annular shaped area having n-sided polygonal boundaries.

REFERENCES:
patent: 4605980 (1986-08-01), Hartranft et al.
patent: 4684967 (1987-08-01), Taylor, Sr. et al.
patent: 4692781 (1987-09-01), Rountree et al.
patent: 4734752 (1988-03-01), Liu et al.
patent: 4745450 (1988-05-01), Hartranft et al.
patent: 4807080 (1989-02-01), Clark
patent: 4819046 (1989-04-01), Misu
patent: 4896243 (1990-01-01), Chatterjee et al.
patent: 4939616 (1990-07-01), Rountree
patent: 5001529 (1991-03-01), Ohshima et al.
patent: 5010380 (1991-04-01), Avery
patent: 5012317 (1991-04-01), Rountree
patent: 5019888 (1991-05-01), Scott et al.
patent: 5077591 (1991-12-01), Chen et al.
patent: 5140401 (1992-08-01), Ker et al.
patent: 5166089 (1992-11-01), Chen et al.
patent: 5182220 (1993-01-01), Ker et al.
patent: 5218222 (1993-06-01), Roberts
patent: 5270565 (1993-12-01), Lee et al.
patent: 5272371 (1993-12-01), Bishop et al.
patent: 5274262 (1993-12-01), Avery
patent: 5289334 (1994-02-01), Ker et al.
patent: 5329143 (1994-07-01), Chan et al.
patent: 5336908 (1994-08-01), Roberts
patent: 5343053 (1994-08-01), Avery
patent: 5389810 (1995-02-01), Agata et al.
patent: 5428238 (1995-06-01), Hayashi et al.
patent: 5429964 (1995-07-01), Yilmaz et al.
patent: 5432371 (1995-07-01), Denner et al.
C. Duvvury and A. Amerasekera, "ESD: A Pervasive Reliability Concern for IC Technologies", Proc. of IEEE, vol. 81, No. 5.pp. 690-702, May 1993.
A. Amerasekera and C. Duvvury, "The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design", 1994 EOS/ESD Symp. Proc., EOS-16, pp. 237-245.
R.N. Rountree, "ESD Protection for Submicron CMOS Circuits: Issues and Solutions", 1988 IEDM Technical Digest, pp.580-583.
R.N. Rountree, C. Duvvury, T. Maki, and H. Stiegler, "A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes", 1988 EOS/ESD Symp. Proc. EOS-10, pp. 201-205.
C. Duvvury, T. Taylor, J. Lindgren, J. Morris, and S. Kumar, "Input Protection Design for Overall Chip Reliability", 1989 EOS/ESD Symp. Proc., EOS-11, pp. 190-197.
G. Rieck and R. Manely, "Novel ESD Protection for Advanced CMOS Output Drivers", 1989 EOS/ESD Symp. Proc., EOS-11, pp. 182-189.
C. Duvvury and R. Rountree, "A Synthesis of ESD Input Protection Scheme", 1991 EOS/ESD Symp. Proc., EOS-13, pp. 88-97.
C.-Y. Wu, M.-D. Ker, C.-Y Lee, and J.Ko, "A New On-Chip ESD Protection Circuit with Dual Parasitic SCR Structures for CMOS VLSI", 1992 IEEE Journal of Solid-State Circuits, vol. 27, No. 3, pp. 274-280.
M.-D. Ker, C.-Y. Wu, and C.-Y. Lee, "A Novel CMOS ESD/EOS Protection Circuit with Full-SCR Structures", 1992 EOS/ESD Symp. Proc., EOS-14, pp. 258-264.
M.-D. Ker and C.-Y. Wu, "CMOS On-Chip Electrostatic Discharge Protection Circuit Using Four-SCR Structures with Low ESD-trigger Voltage", 1994 Solid-State Electronics, vol. 37, No. 1, pp. 17-26.
A. Chatterjee and T. Polgreen, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, vol. 12, No. 1, pp. 21-22, Jan. 1991.
A. Chatterjee and T. Polgreen, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", 1990 Proc. Symposium on VLSI Technology, pp. 75-76.
C. Duvvury, R.N. Rountree, and O. Adams, "Internal Chip ESD Phenomena Beyond the Protection Circuit", IEEE Trans. on Electron Devices, vol. 35, No. 12, pp. 2133-2139, Dec., 1988.
X. Guggenmos and R. Holzner, "A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress", 1991 EOS/ESD Symp. Proc., EOS-13, pp. 74-82.
H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the Series Resistance of On-Chip Power Supply Buses on Internal Device Failure after ESD Stress", IEEE Trans. on Electron Devices, vol. 40, No. 11, pp. 2081-2083, Nov., 1993.
C. Johnson, T.J. Maloney, and S. Qawami, "Two Unusual HBM ESD Failure Mechanisms on a Mature CMOS Process", 1993 EOS/ESD Symp. Proc., EOS-15, pp. 225-231.
C. Duvvury, R. A. McPhee, D. A. Baglee, and R. N. Rountree, "ESD Protection Reliability in 1-.mu.m CMOS Technologies", 1986 IRPS Proc., pp. 199-205.
S. Daniel and G. Krieger, "Process and Design Optimization for Advanced CMOS I/O ESD Protection Devices", 1990 EOS/ESD Symp. Proc., EOS-12, pp. 206-213.
Y. Wei, Y. Loh, C Wang, and C. Hu, "MOSFET Drain Engineering for ESD Performance", 1992 EOS/ESD Symp. Proc., EOS-14 pp. 143-148.
T.L. Polgreen and A. Chatterjee, "Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow", 1992 IEEE Trans. Electron Devices, vol. 39, No. 2, pp. 379-388.
C. Duvvury, C. Diaz, and T. Haddock, "Achieving Uniform nMOS Device Power Distribution for Submicron ESD Reliability", 1992 IEDM Technical Digest, pp. 131-134.
C. Duvvury, and C. Diaz, "Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection", 1992 Proc. of IRPS, pp. 141-150.
Baker, R. Currence, S. Law, M. Le, C. Lee, S.T. Lin & M. Teene, "A Waffle Layout Technique Strengthens the ESD Hardness of the NMOS Output Transistor", 1989 EOS/ESD Symp. Proc. EOS-11, pp. 175-181.
Y.-S. Hu, H.-R. Liauh, and M.-C. Chang, "High Density Input Protection Circuit Design in 1.2 .mu.m CMOS Technology", 1987 EOS/ESD Symp. Proc., EOS-9, pp. 179-185.
S.R. Vemura, "Layout Comparison of MOSFETs With Large W/L Ratios" 1992 Electronics Letters, vol. 28. No. 25, pp. 2327-2329.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

N-sided polygonal cell layout for multiple cell transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with N-sided polygonal cell layout for multiple cell transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and N-sided polygonal cell layout for multiple cell transistor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2050437

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.