N-p butting connections on SOI substrates

Details N-p butting connections on SOI substrates N-p butting connections on SOI substrates

2002-09-17

2004-07-13

abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S351000, C257S370000, C257S371000

Reexamination Certificate

active

06762464

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuits formed on silicon-on-insulator (SOI) substrates.
PRIOR ART
For many years it has been recognized that SOI substrates provide better performing integrated circuits because of the reduced parasitics associated with the thin film silicon layer on which the active devices are formed. Circuits for SOI substrates may be laid out in the same manner as they are for ordinary silicon substrates. However, some benefits can be obtained, as will be described later in this application, where circuits are designed to take advantage of the SOI.
A review first of a current circuit connection and its use in a static random-access memory (SRAM) cell will be helpful in understanding the embodiments of the present invention described later.
In
FIG. 1
, a typical connection from, for instance, a drain region
15
of a p-channel transistor and a drain terminal
14
of a n-channel transistor is shown. First, it should be noted the n-channel transistor is formed in a p-well
11
while the p-channel transistor is formed in an n-well
12
. This arrangement is for a non-SOI substrate
10
. Salicide layers on the regions
14
and
15
include vias which allow the regions
14
and
15
to be connected by a metal line
20
. Generally, a field oxide or trench fill with oxide forms on oxide insulation
13
. This oxide provides separation between the region
14
and the well
12
and between the region
15
and well
14
. Note that without the isolation provided by the oxide
13
, a current path would exist between the region
14
and well
12
, as shown by the arrow
21
and between the region
15
and well
11
, as shown by arrow
22
.
The structure of
FIG. 1
is often used in static random access memory cells where cross coupled inverters, forming a bistable circuit, are used. In
FIG. 2
, the connection of
FIG. 1
is used twice, as shown by the dotted lines
22
and
24
.


REFERENCES:
patent: 5818076 (1998-10-01), Zhang et al.
patent: 5943559 (1999-08-01), Maeda
patent: 6004878 (1999-12-01), Thomas et al.
patent: 6117762 (2000-09-01), Baukus et al.
patent: 6219114 (2001-04-01), Lyu
patent: 6242779 (2001-06-01), Maekawa

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