Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-21
2007-08-21
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10876217
ABSTRACT:
Ports at which a cell served by a local powergrid is to be modeled are designated on a selected metal layer N-levels down from the topmost metal layer of the local powergrid. The cell is modeled at the designated ports, excluding any metal layers above the selected metal layer. Any metal layers of the local powergrid above the selected metal layer are included as part of a model of the global powergrid, rather than as part of the local powergrid, and a hierarchical powergrid analysis is performed.
REFERENCES:
patent: 5878053 (1999-03-01), Koh et al.
patent: 2002/0170020 (2002-11-01), Darden et al.
Zhao, M et al., “Hierarchical analysis of power distribution networks”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on vol. 21, Issue 2, Feb. 2002 pp. 159-168□□.
Qian, H et al., “Hierarchical random-walk algorithms for power grid analysis”, Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific Jan. 27-30, 2004 pp. 499-504□□.
Sheehan, Bernard N., “TICER: Realizable Reduction of Extracted RC Circuits,” iccad, p. 200, 1999 International Conference on Computer-Aided Design (ICCAD '99), IEEE Computer Society, Washington, D.C., 1999.
U.S. Appl. No. 10/876,218, filed Jun. 24, 2004 and naming as inventor(s) Xiaoning Qi, Anuj Trivedi and Kenneth Y. Yan.
Qi Xiaoning
Trivedi Anuj
Yan Kenneth Y.
Bowers Brandon
Chiang Jack
Dorsey & Whitney LLP
Sun Microsystems Inc.
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