N-domino output latch with accelerated evaluate path

Details N-domino output latch with accelerated evaluate path N-domino output latch with accelerated evaluate path

2006-04-25

2006-04-25

Jeanglaude, Jean Bruner (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S095000, C326S098000

Reexamination Certificate

active

07034578

ABSTRACT:
An apparatus and method are provided for accelerating the evaluated output of an N-domino latch. The apparatus includes evaluation N-logic, latching logic, keeper logic, and acceleration logic. The evaluation N-logic is coupled to a first P-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an-evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node. The acceleration logic is coupled and responsive to the pre-charged node and the complementary latch node, and is configured to control the state of an output node.

REFERENCES:
patent: 5045721 (1991-09-01), Yan
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5568069 (1996-10-01), Chow
patent: 5642061 (1997-06-01), Gorny
patent: 5926038 (1999-07-01), Fouts et al.
patent: 6058403 (2000-05-01), Vijayrao et al.
patent: 6060909 (2000-05-01), Aipperspach et al.
patent: 6108805 (2000-08-01), Rajsuman
patent: 6150848 (2000-11-01), Fouts et al.
patent: 6201415 (2001-03-01), Manglore
patent: 6271684 (2001-08-01), Rogenmoser
patent: 6320420 (2001-11-01), Shibayama
patent: 6677783 (2004-01-01), Samaan
patent: 6732336 (2004-05-01), Nystrom et al.
patent: 1130780 (2001-09-01), None

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