N-Channel silicon gate virtual ground ROM

Details N-Channel silicon gate virtual ground ROM N-Channel silicon gate virtual ground ROM

1979-10-05

1982-09-21

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365104, 357 41, 357 45, 357 59, H01L 2710, G11C 1140

Patent

active

043509924

ABSTRACT:
An MOS read only memory or ROM of small cell size is formed by a process compatible with standard N-channel silicon gate ROM manufacturing methods.
In an array of rows and columns of the cells, the row address lines and gates are polysilicon, and column lines forming output and ground are defined by elongated N+ regions which are partly diffused and partly implanted since the column lines cross beneath the polysilicon row address strips. Each potential MOS transistor in the array is programmed to be a logic "1" or a "0" by the presence or absence of moat beneath the gate of a cell.

REFERENCES:
patent: 4021781 (1977-05-01), Caudel
patent: 4151020 (1979-04-01), McElroy
patent: 4207585 (1980-06-01), Rao
patent: 4219836 (1980-08-01), McElroy

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