Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-02-28
2006-02-28
Owens, Douglas W. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
07005711
ABSTRACT:
An n-channel field effect transistor (FET) includes a switchable negative differential resistance (SNDR) characteristic. The n-channel SNDR FET is configured as a depletion mode device, and biased so that it operates essentially as a p-channel device. The device is suitable as a replacement for a p-channel pull-up devices in logic gates (including in inverters) and memory cells.
REFERENCES:
patent: 3903542 (1975-09-01), Nathanson et al.
patent: 3974486 (1976-08-01), Curtis et al.
patent: 4142176 (1979-02-01), Dozier
patent: 4644386 (1987-02-01), Nishizawa et al.
patent: 5023836 (1991-06-01), Mori
patent: 5084743 (1992-01-01), Mishra et al.
patent: 5442194 (1995-08-01), Moise
patent: 5448513 (1995-09-01), Hu et al.
patent: 5455432 (1995-10-01), Hartsell et al.
patent: 5463234 (1995-10-01), Toriumi et al.
patent: 5523603 (1996-06-01), Fishbein et al.
patent: 5552622 (1996-09-01), Kimura
patent: 5654573 (1997-08-01), Oashi et al.
patent: 5732014 (1998-03-01), Forbes
patent: 5761114 (1998-06-01), Bertin et al.
patent: 5798965 (1998-08-01), Jun
patent: 5843812 (1998-12-01), Hwang
patent: 5945706 (1999-08-01), Jun
patent: 5959328 (1999-09-01), Krautschneider et al.
patent: 6015739 (2000-01-01), Gardner et al.
patent: 6075265 (2000-06-01), Goebel et al.
patent: 6084796 (2000-07-01), Kozicki et al.
patent: 6097036 (2000-08-01), Teshima et al.
patent: 6128216 (2000-10-01), Noble, Jr. et al.
patent: 6130559 (2000-10-01), Balsara et al.
patent: 6150242 (2000-11-01), Van der Wagt et al.
patent: 6184539 (2001-02-01), Wu et al.
patent: 6205054 (2001-03-01), Inami
patent: 6222766 (2001-04-01), Sasaki et al.
patent: 6225165 (2001-05-01), Noble, Jr. et al.
patent: 6261896 (2001-07-01), Jun
patent: 6310799 (2001-10-01), Duane et al.
patent: 6353251 (2002-03-01), Kimura
patent: 6396731 (2002-05-01), Chou
patent: 6404018 (2002-06-01), Wu et al.
patent: 6424174 (2002-07-01), Nowak et al.
patent: 6479862 (2002-11-01), King et al.
patent: 6594193 (2003-07-01), King
patent: 6596617 (2003-07-01), King et al.
patent: 6664601 (2003-12-01), King
patent: 2001/0013621 (2001-08-01), Nakazato
patent: 2001/0024841 (2001-09-01), Noble, Jr. et al.
patent: 2001/0053568 (2001-12-01), Deboy et al.
patent: 2002/0017681 (2002-02-01), Inoue et al.
patent: 2002/0048190 (2002-04-01), King
patent: 2002/0054502 (2002-05-01), King
patent: 2002/0057123 (2002-05-01), King
patent: 2002/0063277 (2002-05-01), Ramsbey et al.
patent: 2002/0066933 (2002-06-01), King
patent: 2002/0067651 (2002-06-01), King
patent: 2002/0076850 (2002-06-01), Sadd et al.
patent: 2002/0093030 (2002-07-01), Hsu et al.
patent: 2002/0096723 (2002-07-01), Awaka
patent: 2002/0100918 (2002-08-01), Hsu et al.
patent: 2002/0109150 (2002-08-01), Kajiyama
patent: 0747940 (1996-12-01), None
patent: 0747961 (1996-12-01), None
patent: 0655788 (1998-01-01), None
patent: 1050964 (2000-11-01), None
patent: 1085656 (2001-03-01), None
patent: 1107317 (2001-06-01), None
patent: 0526897 (2001-11-01), None
patent: 1168456 (2002-01-01), None
patent: 1204146 (2002-05-01), None
patent: 8018033 (1996-01-01), None
patent: 2001 01015757 (2001-01-01), None
patent: WO 90/03646 (1990-04-01), None
patent: WO 99/63598 (1999-04-01), None
patent: WO 00/41309 (2000-07-01), None
patent: WO 01/65597 (2001-09-01), None
patent: WO 01/69607 (2001-09-01), None
patent: WO 01/88977 (2001-11-01), None
patent: WO 01/99153 (2001-12-01), None
Barlow, P. S. et al., “Negative differential output conductance of self-heated power MOSFETs,” IEE Proceedings-I Solid-State and Electron Devices, vol. 133, Part 1, No. 5, Oct. 1986, pp. 177-179.
Neel, O. L, et al., “Electrical Translent Study of Negative Resistance in SOI MOS Transistors,” Electronics Letters, vol. 26, No. 1, pp. 73-74, Jan. 1990.
Mohan, S. et al., “Ultrafast Pipelined Adders Using Resonant Tunneling Transistors,” IEE Electronics Letters, vol. 27, No. 10, May 1991, pp. 830-831.
Zhang, J.F. et al., “Electron trap generation in thermally grown SIO2 under Fowler-Nordhelm stress,” J. Appl. Phys. 71 (2), Jan. 15, 1992, pp. 725-734.
Zhang, J.F. et al., “A quantitative Investigation of electron detrapping in SIO2 under Fowler-Northhelm stress,” J. Appl. Phys. 71 (12), Jun. 15, 1992, pp. 5989-5996.
Zhang, J.F. et al., “A comparative study of the electron trapping and thermal detrapping in SIO2 prepared by plasma and thermal oxidation,” J. Appl. Phys. 72 (4), Aug. 15, 1992, pp. 1429-1435.
Luryi, S. et al., “Collector-Controlled States in Charge Injection Transistors,” SPIE-92 Symposium, pp. 1-12, 1992.
Luryi, S. et al., “Collector-Controlled States and the Formation of Hot Electron Domains in Real-Space Transfer Transistors,” AT&T Bell Laboratories, pp. 1-7, 1992.
Luryi, S. et al., “Light-emitting Logic Devices based on Real Space Transfer in Complementary inGaAs/InAIAs Heterostructures”, In “Negative Differential Resistance and Instabilities in 2D Semiconductors”, ed. by N. Balkan, B.K. Ridley, and A. J. Vickers, NATO ASI series [Physics] B 307, pp. 63-82, Plenum Press (New York 1993).
Mohan, S, et al., “Logic Design Based on Negative Differential Resistance Characteristics of Quantum Electronic Devices,” IEE Proceedings-G: Electronic Devices, vol. 140, No. 6, Dec. 1993, pp. 383-391.
Mohan, S. et al., “Ultrafast Pipelined Arithmetic Using Quantum Electronic Devices,” IEE Proceedings-E: Computers and Digital Techniques, vol. 141, No. 2, Mar. 1994, pp. 104-110.
Chan, E. et al., “Compact Multiple-Valued Multiplexers Using Negative Differential Resistance Devices,” IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 1996, pp. 1151-1156.
Chan, E. et al., “Mask Programmable Multi-Valued Logic Gate Using Resonant Tunnelling Diodes,” IEE Proceedings-Circuits Devices Syst., vol. 143, No. 5, Oct. 1996, pp. 289-294.
Shao, Z. et al., “Transmission Zero Engineering in Lateral Double-Barrier Resonant Tunneling Devices,” Dept. of Electrical Engineering, University of Notre Dame, pp. 1-7 (1996).
Goldhaber-Gordon, David et al., “Overview of nanoelectronic devices,” Proc. IEEE, 85(4), Apr. 1997, pp. 521-540.
Koester, S. J. et al., “Negative Differential Conductance in Lateral Double-Barrier Transistors Fabricated in Strained Si Quantum Wells,” Applied Physics Letters, vol. 70, No. 18, May, 1997, pp. 2422-2424.
Dozsa, L. et al., “A transient method for measuring current-voltage characteristics with negative differential resistance regions,” Research Institute for Technical Physics, P.O. Box 76, H-1325 Budapest, Hungary, (Receieved Jul. 24, 1997; accepted Aug. 1, 1997), 2 pages.
Pacha, C. et al., “Design of Arithmetic Circuits using Rsonant Tunneling Diodes and Threshold Logic,” Lehrstuhl Bauelemente der Elektrotechnik, Universitat Dortmund, pp. 1-11, Sep. 1997.
Hansch, W. et al., “The planar-doped-barrier-FET: MOSFET overcomes conventional limitations,” ESSDERC'97 27TH European Solid-State Device Research Conference, Stuttgart, Sep. 22-24, 1997, 4 pages.
Wirth, G. et al., “Periodic transconductance oscillations in sub-100nm MOSFETs,” ESSDERC'97 27th European Solid-State Device Research Conference, Stuttgart, Sep. 22-24, 1997, 4 pages.
Haddad, G.I. et al., “Tunneling Devices and Applications in High Functionality/Speed Digital Circuits,” Solid State Electronics, vol. 41, No. 10, Oct. 1997, pp. 1515-1524.
Gardner, C. et al., “Smooth Quantum Hydrodynamic Model Simulation of the Resonant Tunneling Diode,” Dept. of Mathematics Arizona State University, pp. 1-5, (1998).
Jungel, A. et al., “Numerical Simulation of Semiconductor Devices: Energy-Transport and Quantum Hydrodynamic Modeling,” Fachberelch Math., Tech. Univ. Berlin, Germany, pp. 1-9, 1998.
Nimour, S. M. A. et al., “Effect of Spatially Disordered Barriers on the Band Structure of Finite Superlattices,” phys. stat. sol. (b) 1998, 209, No. 2, 311-318.
Rommel,
Bever Hoffman & Harms LLP
Harms Jeanette S.
Owens Douglas W.
Progressant Technologies, Inc.
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