N-channel LDMOS with buried p-type region to prevent...

Details N-channel LDMOS with buried p-type region to prevent... N-channel LDMOS with buried p-type region to prevent...

2005-10-25

2005-10-25

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S333000, C257S339000

Reexamination Certificate

active

06958515

ABSTRACT:
An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

REFERENCES:
patent: 4922327 (1990-05-01), Mena et al.
patent: 6137140 (2000-10-01), Efland et al.
patent: 6150671 (2000-11-01), Harris et al.
patent: 6437399 (2002-08-01), Huang

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