(N+1) input flip-flop packing with logic in FPGA architectures

Details (N+1) input flip-flop packing with logic in FPGA architectures (N+1) input flip-flop packing with logic in FPGA architectures

2011-05-17

2011-05-17

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C326S041000

Reexamination Certificate

active

07944238

ABSTRACT:
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

REFERENCES:
patent: 7701250 (2010-04-01), Kaptanoglu
patent: 2005/0275428 (2005-12-01), Schlacter
patent: 2007/0075742 (2007-04-01), Feng et al.

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