Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-14
2001-10-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S928000, C257S382000
Reexamination Certificate
active
06300661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a mutual implant region formed within a well which is shared by a source region of a transistor and a well-tie region coupled to the well, thereby providing high integration density for the integrated circuit.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (“MOS”) device are generally well known. A MOS transistor typically comprises a date conductor spaced above a semiconductor substrate by a gate dielectric. The gate conductor is typically patterned from a layer of polysilicon using various lithography techniques. The substrate generally comprises a lightly doped monolithic silicon-based wafer. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define junctions which are also known as source/drain regions. A “well” which is doped opposite the bulk substrate may exist within a portion of the substrate to accommodate junctions of an impurity type opposite that of the junctions formed in the non-well areas. A typical n-channel MOS (“NMOS”) transistor employs n-type junctions placed into a p-type substrate or a p-type well of an n-type substrate. Conversely, a typical p-channel MOS (“PMOS”) transistor comprises p-type junctions placed into an n-type substrate or an n-type well of a p-type substrate. Wells are often employed when both n-type and p-type transistors are needed to form a complementary MOS (“CMOS”) circuit.
Fabrication of an integrated circuit involves placing numerous multiple-input logic devices above and within a semiconductor substrate. Different logic devices employ different configurations of MOS transistors.
FIG. 1
depicts an exemplary logic device known as the NAND gate in symbolic form. Although
FIG. 1
shows the NAND gate as having only two inputs, A
IN
and B
IN
, a NAND gate may have several inputs.
FIG. 2
depicts the circuit diagram of the NAND gate in FIG.
1
. As shown, the NAND gate includes a pair of PMOS transistors
10
connected in parallel and a pair of NMOS transistors
12
connected in series. The source of the lower-most transistor
12
is connected to ground, and the source of each transistor
10
is connected to a VCC voltage, i.e., a power source.
FIG. 3
illustrates a cross-sectional view of a portion of a NAND gate which embodies NMOS series-connected transistors
12
. A p-type well
16
resides within an n-type substrate
14
. Well
16
is bounded between trench isolation structures
17
. A p-type implant region
18
is arranged within well
16
. Implant region
18
has been implanted with a higher concentration of p-type species (often referred to as a p
+
implant) than has well
16
. Implant region
18
thusly formed is often referred to as a “well-tie” implant region which serves as a low resistive path from a contact
28
to well
16
. A source region
20
of one transistor
12
is laterally spaced from implant region
18
and from a common source/drain region
22
shared by both transistors
12
. Source/drain region
22
functions as a drain for one transistor and as a source for another transistor of the series-connected transistors
12
. A drain region
24
of the other transistor
12
is laterally spaced from source/drain region
22
within well
16
.
An interlevel dielectric
26
which serves to isolate transistors
12
extends across the transistors and substrate
14
. Contacts
28
,
30
, and
32
which comprise a conductive material extend vertically through a portion of interlevel dielectric
26
to implant region
18
, source region
20
, and drain region
24
, respectively. Ground conductors
34
and
35
extend horizontally across interlevel dielectric
26
, electrically linking contacts
28
and
30
to ground. Coupling well-tie implant region
18
to ground conductor
34
affords biasing p-well
16
to ground, and thereby inhibits forward biasing the p-well, and thereby prevents current from flowing from well
16
to the bulk of substrate
14
. Otherwise, current might inadvertently flow from well
16
to other devices residing in substrate
14
, rendering the integrated circuit inoperable. Applying ground voltage to source region
20
biases the source region relative to source/drain region
22
. Assuming that the gate-to-source voltages of n-channel transistors
12
exceed the transistor threshold voltage for each respective transistor, biasing source
20
will allow adequate gate voltages to cause drive current to flow from drain region
24
to source region
20
. An output conductor
36
into which the drive current (i.e., load sink current) of the NAND gate may be measured is connected to drain region
24
through contact
32
.
A pervasive trend in modern integrated circuit manufacturing is to produce more complex integrated circuits which operate at higher frequencies (i.e., quickly transition between logic states). Unfortunately, the packing density of an integrated circuit limits the amount of complexity that can be achieved for an integrated circuit. While the well-tie implant region is a critical feature of an integrated circuit which employs wells, it undesirably occupies valuable space within a substrate and/or well of limited lateral area. Moreover, the contact and conductor coupled to the well-tie region increase the amount of space required to bias a well. While reducing the sizes of the contact and the conductor would increase the packing density of the integrated circuit, this is not possible because of the limitations of optical lithography. It is well known that the dimensions of features, e.g., contacts and conductors, patterned using lithography cannot be reduced beyond a lower limit. Also, decreasing the lateral area occupied by a well-tie region is not a viable option because doing so would lead to an undesirable increase in the resistance of the well-tie region.
It would therefore be of benefit to develop a technique for reducing the amount of space required to bias a well residing within a semiconductor substrate. That is, the lateral area occupied by only the well-tie region within the well needs to be reduced. However, to avoid an unwanted increase in the resistance to the pathway of current flowing from a contact coupled to the well-tie region to the well, the dimensions of the well-tie region itself cannot be reduced significantly. Moreover, it would also be desirable to reduce the amount of space occupied by the contact and the conductor connected to the well-tie region. Absent the ability to reduce the dimensions of the contact and the cconductor, other measures must be taken to increase the packing density of those elements within the integrated circuit. Therefore, it would be beneficial to improve the layout scheme of conventional well and source contacts by merging the well-tie region, the contact coupled to the well-tie region, and the conductor connected to the contact with other elements of an integrated circuit. Decreasing the space occupied by only those elements used to bias the well would advantageously improve the packing density of the integrated circuit, providing for higher circuit complexity.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for forming a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well. According to a preferred embodiment, a single electrical link is provided to the well and the source region. Several contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, the conductor may be, rounded to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be ap
Duane Michael P.
Gardner Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Prenty Mark V.
LandOfFree
Mutual implant region used for applying power/ground to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mutual implant region used for applying power/ground to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mutual implant region used for applying power/ground to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2551775