Multiway associative external microprocessor cache

Details Multiway associative external microprocessor cache Multiway associative external microprocessor cache

1997-06-12

1999-06-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711129, 711140, 711154, G06F 1314

Patent

active

059096942

ABSTRACT:
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A multiway cache includes a single array partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding data is accessed from alternate slots while searching said directory, thereby reducing the latency penalty for cache access.

REFERENCES:
patent: 4695943 (1987-09-01), Keeley
patent: 4905141 (1990-02-01), Brenza
patent: 4905188 (1990-02-01), Chuang et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5313605 (1994-05-01), Huck et al.
patent: 5392410 (1995-02-01), Liu
patent: 5416739 (1995-05-01), Wong
patent: 5418922 (1995-05-01), Liu
patent: 5450565 (1995-09-01), Nadir et al.
patent: 5479641 (1995-12-01), Nadir et al.
patent: 5488709 (1996-01-01), Chan
patent: 5619676 (1997-04-01), Fukuda
patent: 5664147 (1997-09-01), Mayfield
patent: 5737750 (1998-04-01), Kumar
patent: 5778436 (1998-07-01), Kedem
patent: 5793693 (1998-08-01), Collins
"Associative Scheme for Cache Coherence in Multi-Processors", IBM Technical Disclosure Bulletin, vol. 39, No. 5, May 1996, pp. 153-156.
"The Correlation Branch Target Address Cache", IBM Technical Disclosure Bulletin, vol. 39, No. 05, May 1996, pp. 83-85.
"Computer Memory Organization Using Fast Nonvolatile Storage", IBM Technical Disclosure Bulletin, vol. 35, No. 1B, Jun. 1992, pp. 380-382.
Farkas, K.I. et al. "How Useful are Non-blocking Loads . . . ?" Proceedings, 1st IEEE Symposium on High Performance Computer Architecture, IEEE Comp.Soc.Pres, xii, pp. 78-89, 1995. INSM abstract AN4881199.
Ooi, Y., et al. "Fault-tolerant Architecture in a Cache Memory Control LSI", IEEE J. Solid-State Circuits, v. 27 n. 4 pp. 507-514 Apr. 1992. INSM abstract AN 4165931.

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