Multithreading implementation for flops and register files

Details Multithreading implementation for flops and register files Multithreading implementation for flops and register files

2011-06-07

2011-06-07

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

07958323

ABSTRACT:
A processor having a multithreading memory system, including a main memory element, at least one special memory element and a controller. The main memory element may be configured to receive a data signal and a control signal. The at least one special memory element may be associated with the main memory element. Further, the special memory element may be configured to receive an output signal from the main memory element. The controller may be configured to receive an output signal from the at least one special memory element and a scan input signal. Further, the controller may be further configured to select one of the output signal from the at least one special memory element and the scan input signal based on an advance thread signal. The selected one of the output signal from the at least one special memory element and the scan input signal may be forwarded to the main memory element as the control signal.

REFERENCES:
patent: 6681345 (2004-01-01), Storino et al.
patent: 6785890 (2004-08-01), Kalafatis et al.
patent: 7143267 (2006-11-01), Fluhr et al.
patent: 7185185 (2007-02-01), Joy et al.
patent: 7316021 (2008-01-01), Joy et al.

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