Multithreaded clustered microarchitecture with dynamic...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S100000, C711S154000, C712S001000

Reexamination Certificate

active

07996617

ABSTRACT:
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

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J.M. Borkenhagen et al., “A multithreaded PowerPC processor for Commercial Servers”, IBM Journal of Research and Development, vol. 44, No. 6, p. 885 (2000), Advanced Microprocessor design, Copyright 2000 IBM, pp. 885-898.

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