Multitask processor architecture having a plurality of instructi

Details Multitask processor architecture having a plurality of instructi Multitask processor architecture having a plurality of instructi

1994-05-24

1997-02-04

Kriess, Kevin A.

Boots, shoes, and leggings

3642282, 3642303, 364DIG1, 395677, G06F 906

Patent

active

056008376

ABSTRACT:
A processor architecture for executing a current task among a plurality of possible tasks. The architecture includes: a plurality of instruction pointers respectively associated with the tasks and each storing the address of the current instruction to be executed of the associated task, only one of these pointers being enabled at a time to supply an address to the memory; a priority level decoder including circuitry for assigning a predetermined priority level to each request signal and for enabling the instruction pointer associated with the active request signal having the highest priority level; and a mechanism for incrementing the content of the enabled instruction pointer and for reinitializing it at the start address of the associated program when its content reaches the end address of the associated program.

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The 19th Annual International Symposium on Computer Architecture, May 19-21, 1992, Gold Coast Australia, "An Elementary Processor Architecture with Simultaneous Instruction Issuing From Multiple Threads", pp. 136-145.
The 17th Annual International Symposium on Computer Architecture, May 28-31, 1990, Seattle, WA IEEE Computer Society Press, Los Alamitos, CA, "April: A Processor Architecture for Multiprocessing" Anant Agarwal, et al., pp. 104-114.
The 15th Annual International Symposium on Computer Architecture, May 30-Jun. 2, 1988, Honolulu, Hawaii, IEEE Computer Society, "MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing", Robert H. Halsted, Jr., et al., pp. 443-451.
1994 International Conference on Parallel and Distributed Systems, IEEE Computer Society Press, Los Alamitos, CA, "A Fast Switching Double Processing Architecture for Multi-Tasking Real-Time Systems", Tein-Hsiang Lin, et al., pp. 82-87.

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