Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
1994-02-25
2001-10-16
Winder, Patrice (Department: 2155)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S233000
Reexamination Certificate
active
06304957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a microcomputer which is equipped with the function of time shared parallel processing of plural programs.
2. Description of the Related Arts
Some of the recent microcomputers are designed to perform a time shared parallel processing of plural tasks by changing over the multi task processing in consecutive order by means of a register counter or a multiplexer as described, for instance, in the Japanease Patent Publication laid-open No. 58-155406, and No. 59-191654. In those conventional compositions, an exclusive hard timer is required to perform time processing by letting the elapsed time known when a task is executed. In addition, it is necessary to provide externally a runaway monitoring logic like a watchdog timer to monitor the runaway of program of each task, which contributes, combined with the above-mentioned matter, to making the peripheral circuits of a microcomputer complicated, leading to the product becoming larger-sized and more expensive.
Furthermore, in the conventional compositions, an erroneous jump to the address of other task and the execution of its instruction occurs due to an unexpected cause like noise. In the past, a reset method employed in such a case has been to provide a runaway monitoring logic such as a watchdog timer in the peripheral circuits, which involves time loss before a runaway is detected since it has to be monitored externally, and a risk of the memory data or port data being destroyed in the meantime.
Furthermore, the pipeline processing in the conventional microcomputers has the problem of there occurring pipeline disturbances when a branch instruction is executed, causing at least one wasteful cycle, i.e. delayed cycle, thereby delaying the pipeline processing. The cause of this wasteful cycle occurring after a branch instruction in the conventional pipeline processing is that if the branch instruction is fetched, the instruction address to be fetched next is predetermined in order beforehand regardless of the branch address, and the instruction of the branch address can be fetched only after this wasteful instruction is fetched.
In the past, it has been possible that the multiple-word instruction system with an unfixed number of instruction words, e.g. instruction system in which there are one-word instruction as well more than two-word instruction, can interpret an instruction wrongly due to mis-perception of the operation code or operand, thereby causing a program runaway or mass destruction of important information in data memory.
It is further possible for the program address to branch out to the address in the table immediate data area provided in the program memory, and an execution is started by perceiving the table immediate data as operation code, which also causes a program runaway or mass destruction of important information in data memory. On this account, it has been also necessary, in the past, to install a runaway monitoring logic such as a watchdog timer in the peripheral circuits, which contributes to making the peripheral circuits of a microcomputer complicated, resulting in the product becoming larger-sized and more expensive. Furthermore, the installation of a runaway monitoring logic such as a watchdog timer involves time loss before a runaway is detected since it has to be monitored externally, and a risk of the memory data or port data being destroyed in the meantime.
SUMMARY OF THE INVENTION
An object of this invention is to provide a microcomputer in which simplification of the peripheral circuits, reduction in price and facility of design alteration can be realized, besides being equipped with the function of timer or runaway monitoring.
Another object of this invention is to provide a microcomputer which can detect a branching by error to the address of other task due to an unexpected cause like noise in the multitask processing in much quicker response than the external monitoring method by means of such as a watchdog timer.
Still another object of this invention is to provide a microcomputer which can perform a pipeline processing quickly and without delay if there is a branch instruction.
Furthermore, it is also an object of this invention to provide a microcomputer which can prevent a data destruction if there occurs mis-perception of the operation code/operand or address error.
The primary feature of the multitask processing unit of this invention is that it is equipped with the function to perform a parallel processing by switching plural programs for every several cycles in a certain time division, an instruction cycle condition memory means which, in the case of an instruction being on the way of execution when the program is switched, will retain the midway instruction to start execution from the midway condition at the time of the next execution cycle of the program in which said instruction is contained. It will allow a switch of plural programs in a certain cycle division ratio, not depending on the necessary cycle of the instruction, thereby securing the independence between the plural programs in terms of time.
In this case, if a branch instruction is prohibited for a specific program in the plural programs and a composition is employed in which a fixed loop execution is performed from the starting address to the specified address, incorporating in the said specific program the routine of at least either of the runaway monitor or the timer function, the specific program can, in the condition in which the program runaway or deadlock is prohibited by the fixed-looping, perform the runaway monitoring or timer operation of the programs of other task, allowing omission of the runaway monitoring logic in the peripheral circuits, hard timer or interrupt logic. It can also realize the facility of design alteration.
The secondary feature of the multitask processing unit of this invention is that it is equipped with the function to perform a parallel processing by switching plural programs for every several cycles in a certain time division, with each instruction of the said plural programs being added with the task identification bit to identify the kind of program, enabling an error check to be performed according to the contents of the said task identification bit after the reading of instruction. It allows to detect quickly a branching to the address of other task by error due to an unexpected cause like noise. In the case of two tasks, a parity bit can be used as task identification bit.
The third feature of the multitask processing unit of this invention is that it will perform a pipeline processing of the plural task programs in parallel by time division, a pipeline processing quick and without delay by using the wasteful cycle after the branch instruction contained in one program for another program. That is, it will perform a pipeline processing in parallel by switching plural programs for every several cycles in a certain time division, and, when a branch instruction is fetched, finish the execution (setting at the branch destination) one cycle before the instruction fetch stage following the program which contains said branch instruction, allowing to fetch the instruction of the branch address at the instruction fetch stage following the program which contains the said branch instruction. It eliminates the occurrence of a wasteful cycle in the pipeline if there is a branch instruction and prevents the pipeline from delaying.
The forth feature of the multitask processing unit of this invention is that, in the case of a unit which incorporates the data area for operation in the memory containing a program, there is installed in each instruction of the program a caution-requiring instruction discrimination bit composed of a small number of bits in said instruction which indicates a character of the instruction whether it is possible for the instruction to lead to a program runaway, while giving to the data in the data area a caution-requiring instruction discrimination bit provided with the value to indicate a non
Ishihara Hideaki
Maeda Kouichi
Nippondenso Co. Ltd.
Pillsbury & Winthrop LLP
Winder Patrice
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