Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2003-08-18
2008-10-14
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C711S158000, C712S003000, C712S040000, C712S225000
Reexamination Certificate
active
07437521
ABSTRACT:
A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.
REFERENCES:
patent: RE28577 (1975-10-01), Schmidt
patent: 4412303 (1983-10-01), Barnes et al.
patent: 4541046 (1985-09-01), Nagashima et al.
patent: 4771391 (1988-09-01), Blasbalg
patent: 4868818 (1989-09-01), Madan et al.
patent: 4888679 (1989-12-01), Fossum et al.
patent: 4933933 (1990-06-01), Dally et al.
patent: 4989131 (1991-01-01), Stone
patent: 5008882 (1991-04-01), Peterson et al.
patent: 5031211 (1991-07-01), Nagai et al.
patent: 5036459 (1991-07-01), Den Haan et al.
patent: 5068851 (1991-11-01), Bruckert et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5157692 (1992-10-01), Horie et al.
patent: 5161156 (1992-11-01), Baum et al.
patent: 5170482 (1992-12-01), Shu et al.
patent: 5175733 (1992-12-01), Nugent
patent: 5197130 (1993-03-01), Chen et al.
patent: 5218601 (1993-06-01), Chujo et al.
patent: 5218676 (1993-06-01), Ben-ayed et al.
patent: 5239545 (1993-08-01), Buchholz
patent: 5247635 (1993-09-01), Kamiya
patent: 5247691 (1993-09-01), Sakai
patent: 5276899 (1994-01-01), Neches
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5313628 (1994-05-01), Mendelsohn et al.
patent: 5313645 (1994-05-01), Rolfe
patent: 5331631 (1994-07-01), Teraslinna
patent: 5333279 (1994-07-01), Dunning
patent: 5341504 (1994-08-01), Mori et al.
patent: 5347450 (1994-09-01), Nugent
patent: 5353283 (1994-10-01), Tsuchiya
patent: 5365228 (1994-11-01), Childs et al.
patent: 5375223 (1994-12-01), Meyers et al.
patent: 5418916 (1995-05-01), Hall et al.
patent: 5430850 (1995-07-01), Papadopoulos et al.
patent: 5430884 (1995-07-01), Beard et al.
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5440547 (1995-08-01), Easki et al.
patent: 5446915 (1995-08-01), Pierce
patent: 5517497 (1996-05-01), LeBoudec et al.
patent: 5530933 (1996-06-01), Frink et al.
patent: 5546549 (1996-08-01), Barrett et al.
patent: 5548639 (1996-08-01), Ogura et al.
patent: 5550589 (1996-08-01), Shiojiri et al.
patent: 5555542 (1996-09-01), Ogura et al.
patent: 5560029 (1996-09-01), Papadopoulos et al.
patent: 5640524 (1997-06-01), Beard et al.
patent: 5649141 (1997-07-01), Yamazaki
patent: 5684977 (1997-11-01), Van Loo et al.
patent: 5717895 (1998-02-01), Leedom et al.
patent: 5721921 (1998-02-01), Kessler et al.
patent: 5765009 (1998-06-01), Ishizaka
patent: 5787494 (1998-07-01), Delano et al.
patent: 5796980 (1998-08-01), Bowles
patent: 5835951 (1998-11-01), McMahan
patent: 5860146 (1999-01-01), Vishin et al.
patent: 5897664 (1999-04-01), Nesheim et al.
patent: 5987571 (1999-11-01), Shibata et al.
patent: 6003123 (1999-12-01), Carter et al.
patent: 6014728 (2000-01-01), Baror
patent: 6088701 (2000-07-01), Whaley et al.
patent: 6101590 (2000-08-01), Hansen
patent: 6105113 (2000-08-01), Schimmel
patent: 6161208 (2000-12-01), Dutton et al.
patent: 6308316 (2001-10-01), Hashimoto et al.
patent: 6317819 (2001-11-01), Morton
patent: 6339813 (2002-01-01), Smith, et al.
patent: 6356983 (2002-03-01), Parks
patent: 6430649 (2002-08-01), Chaudhry et al.
patent: 6490671 (2002-12-01), Frank et al.
patent: 6496902 (2002-12-01), Faanes et al.
patent: 6496925 (2002-12-01), Rodgers et al.
patent: 6519685 (2003-02-01), Chang
patent: 6591345 (2003-07-01), Seznec
patent: 6665774 (2003-12-01), Faanes et al.
patent: 6684305 (2004-01-01), Deneau
patent: 6782468 (2004-08-01), Nakazato
patent: 6816960 (2004-11-01), Koyanagi
patent: 6922766 (2005-07-01), Scott
patent: 6925547 (2005-08-01), Scott et al.
patent: 6976155 (2005-12-01), Drysdale et al.
patent: 7028143 (2006-04-01), Barlow et al.
patent: 7334110 (2008-02-01), Faanes, et al.
patent: 7366873 (2008-04-01), Kohn
patent: 2002/0116600 (2002-08-01), Smith et al.
patent: 2002/0169938 (2002-11-01), Scott et al.
patent: 2002/0172199 (2002-11-01), Scott et al.
patent: 2003/0005380 (2003-01-01), Nguyen et al.
patent: 2003/0097531 (2003-05-01), Arimilli, et al.
patent: 2003/0167383 (2003-09-01), Gupta et al.
patent: 2005/0044128 (2005-02-01), Scott et al.
patent: 2005/0044339 (2005-02-01), Sheets
patent: 2005/0044340 (2005-02-01), Sheets et al.
patent: 2007/0283127 (2007-12-01), Kohn, et al.
patent: 0353819 (1990-02-01), None
patent: 0473452 (1992-03-01), None
patent: 0475282 (1992-03-01), None
patent: 0501524 (1992-09-01), None
patent: 0570729 (1993-11-01), None
patent: WO-87/01750 (1987-03-01), None
patent: WO-88/08652 (1988-11-01), None
patent: WO-95/16236 (1995-06-01), None
patent: WO-96/10283 (1996-04-01), None
patent: WO-96/32681 (1996-10-01), None
US 7,243,211, 07/2007, Kohn (withdrawn)
“Deadlock-Free Routing Schemes on Multistage Interconnection Networks”,IBM Technical Disclosure Bulletin, 35, (Dec. 1992),232-233.
Adve, V. S., et al., “Performance Analysis of Mesh Interconnection Networks with Deterministic Routing”,Transactions on Parallel and Distributed Systems, (Mar. 1994),225-246.
Bolding, Kevin , “Non-Uniformities Introduced by Virtual Channel Deadlock Prevention”,Technical Report 92-07-07, Department of Computer Science and Engineering, FR-35 University of Washington; Seattle, WA 98195 (Jul. 21, 1992).
Bolla, F R., “A Neural Strategy for Optimal Multiplexing of Circuit and Packet-Switched Traffic”,Department of Communications, Computer and Systems Science(DIST),University of Genova, 1324-1330.
Boura, Y M., et al., “Efficient Fully Adaptive Wormhole Routing in n- dimenstional Meshes”,IEEE, (1994),589-596.
Bundy, A. , et al., “Turning Eureka Stepsinto Calculations in Automatic Program”,UK IT, (IEE Conf. Pub. 316), (1991),221-226.
Chien, A. A., et al., “Planar-Adaptive Routing: Low-Cost Adaptive Networks for Multiprocessors”,Pro. 19th International. Symposium on Computer Architecture, (May 1992),268-277.
Dally, W. J., et al., “Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels”,I.E.E.E. Transactions on Parallel and Distributed Systems, 4(4), (Apr. 1993),466-475.
Dally, William , et al., “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks”,IEEE Transactions on Computers, C-36, (May 1987),547-553.
Dally, William , “Performance Analysis of k-ary n-cube Interconnection Networks”,IEEE Transactions on Computers, 39(6), (Jun. 1990),775-785.
Dally, W. J., “Virtual Channel Flow Control”,Pro. 17th International Symposium on Computer Architecture, pp. 60-68, May 1990.
Duato, J. , “A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks”,I.E.E.E. Transactions on Parallel and Distributed Systems, 4(12), (Dec. 1993),1320-1331.
Faanes, G. J., et al., “Decoupled Vector Architecture”, U.S. Appl. No. 10/643,586, filed Aug. 18, 2003, 47 Pages.
Gallager, Robert , “Scale Factors for Distributed Routing Algorithm”,NTC '77 Conference Record, 2, at 2-1 through 2-5.
Gharachorloo, Kourosh , “Two Techniques to Enhance the Performance of Memory Consistency Models”, (1991).
Glass, C. J., et al., “The Turn Model for Adaptive Routing”,Pro. 19th International Symposium on Computer architecture, (May 1992),278-287.
Gravano, L , et al., “Adaptive Deadlock- and Livelock-Free Routing with all Minimal Paths in Torus Networks”,IEEE Transactions on Parallel and Distributed Systems, 5(12), (Dec. 199
Faanes Gregory J.
Kohn James R.
Moore, Jr. William T.
Scott Steven L.
Stephenson Brick
Cray Inc.
Savla Arpan
Schwegman Lundberg & Woessner, P.A.
Shah Sanjiv
LandOfFree
Multistream processing memory-and barrier-synchronization... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multistream processing memory-and barrier-synchronization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistream processing memory-and barrier-synchronization... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4000971