Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-06-11
2001-08-21
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S218000, C365S185290, C365S238500
Reexamination Certificate
active
06279070
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a multi-step pulse generating circuit and a method of erasing a flash memory using the same which can reduce the erasing time for the flash memory.
2. Description of the Prior Art
Generally, the procedure of erasing the flash memory cell includes a pre-program step, an erase step and a post-program step. Recently, a multi-step pulse erase method is used to improve the threshold voltage level of the erased memory cell.
However, though the multi-step pulse erase method can improve the threshold voltage level of the memory cell, it has a disadvantage that requires a lot of time since it has to perform pumping in multi-steps. Actually, the pumping, in erasing one sector using the multi-step pulses, requires the time of about 200 ms. Thus, it has a disadvantage that the time of 1400 ms is consumed only for the pumping because there are seven sectors for the memory chip of 200 Mb.
In addition, in case that the suspense command is input during the erasure operation, the erase operation new being performed is suspended and a read mode is then performed. Then, the erase operation is resumed by means of the resume command. However, it has a disadvantage that information on the previous pumping number cannot be found since the block for counting the pumping number of the multi-step pulses in reset upon transformation into the read mode. In other words, when the erase operation is resumed, it requires the time of about 200 ms for the multi-step words, when the erase operation is resumed, it requires the time of about 200 ms for the multi-step pulse erase in one sector since the multi-step erase operation has to be performed from the start. Also, when resuming the erase operation, if the multi-step pulse erase procedure is emitted, the multi-step pulse erase is meaningless.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a multi-step pulse generating circuit and a method of erasing a flash memory using the same, which can shorten the erase time for the flash memory and reduce the size of a device, in a way that it stores the information at the time when the suspense command is input during the multi-step pulse erase operation, switches it into a read mode, and resumes the erase operation from the time when the information is stored.
In order to accomplish the above object, the multi-step pulse generating circuit is characterized by comprising loop counter for counting the number of repeating eras or program operation based or a loop reset signal output a loop reset circuit when a fail cell is occurred during said erase or program operation, and then generating a multi-step pulse erase mode signal in response to the number of counting; timer for generating pulse signals of appropriate intervals for respective erase modes in response to said multi-step erase mode signal generated from said loop counter; multi-step pulse generating block for outputting a multi-step erase signal, and either a multi-step pulse erase signal or a normal erase signal, based on said multi-step pulse erase mode signal output from said loop counter, said pulse signal output from said timer, an erase mode signal, and an erase reset signal; and pulse generating number counter for counting the number of toggling said pulse signal output from said timer, for generating an erase reset signal to reset said multi-step pulse generating block when a given number of counting is reached, and for storing the counting number at the time when a suspense command is input if said suspense command is input during said multi-step pulse erase mode, and for resuming said multi-step erase mode from the time when the suspense command is stored.
The method of erasing a flash memory cell according to the present invention consists of a pre-program, an erase process and a post-program process, the method comprising the steps of checking whether the present mode is a multi-step pulse erase mode or not, and if so, generating the multi-step pulse to perform the multi-step erase operation; during the multi-step pulse erase operation, confirming at first times whether a suspense command has been input or not, if the suspense command was input, suspending the multi-step pulse erase operation and then incrementing the count of a loop count without resetting a pulse generating number counter, and if the suspense command was not input, resetting the pulse generating number counter and then increment the count of the loop counter, as a result of confirming at second times whether the suspense command has been input or not, if the suspense command was input, resetting the count of the loop counter and then confirming whether the suspense command has been input or not at third times; as a result of confirming at second times whether the suspense command has been input or not, if the suspense command was not input, verifying the erase result, then if the erase operation was not successfully performed, proceeding to the step confirming whether it is the multi-step pulse erase mode or not, and if the erase operation was successfully performed, proceeding to the step which resets the loop counter; as a result of confirming at third times whether the suspense command has been input or not, if the suspense command was input, confirming whether a resume command has been input or not, and if the suspense command was not input, performing the post program process; as a result of confirming whether the resume command has been input or not if, the resume command was input, using the preserved count to resume the multi-step pulse erase operation, if the resume command was not input, switching a read mode; and as a result of checking whether it is the multi-step pulse erase mode or not, if is the normal erase mode not the multi-step pulse erase mode, pumping the voltage level by an erase voltage and then performing the normal erase operation.
According to the present invention, in order to solve a problem of requiring a lot of time since the multi-step pulse generating procedure has to be performed from the start, especially when the erase operation is resumed after being suspended by the suspense command during the erase operation, it switches the information at the time when the erase procedure is suspended by the suspense command into a read mode without resetting the information, and then resumes the erase operation based on the information stored at the time when the suspense command is input upon resuming the erase operation.
REFERENCES:
patent: 5724303 (1998-03-01), Gannage et al.
patent: 5805501 (1998-09-01), Shiau et al.
patent: 5835414 (1998-10-01), Hung et al.
patent: 5862099 (1999-01-01), Gannage et al.
patent: 5890193 (1999-03-01), Chevallier
patent: 4-206094 (1992-07-01), None
patent: 4-279298 (1992-10-01), None
patent: 5-028775 (1993-02-01), None
patent: 5-159586 (1993-06-01), None
patent: 6-150675 (1994-05-01), None
patent: 6-187791 (1994-07-01), None
patent: 6-244386 (1994-09-01), None
patent: 6-332797 (1994-12-01), None
patent: 8-180694 (1996-07-01), None
Jeong Jae Heon
Lee Jong Seuk
Hyundai Electronics Industries Co,. Ltd.
Pennie & Edmonds LLP
Peugh Brian R.
Thai Tuan V.
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