Static information storage and retrieval – Read/write circuit – Parallel read/write
Reexamination Certificate
2006-05-30
2006-05-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Parallel read/write
C365S194000, C365S233100, C365S189011, C365S230080
Reexamination Certificate
active
07054215
ABSTRACT:
Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages (1710) of latches through which the parallel data is transferred before being read out serially. The multiple stages provide suitable delays to satisfy variable latency requirements (e.g. CAS latency in DDR2). The first bit for the serial output bypasses the last stage (1710.M). In some embodiments, the control signals controlling the stages other than the last stage in their providing the first data bit to the memory output are not functions of the control signals controlling the last stage providing the subsequent data bits to the memory output.
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Eaton Steve S.
Kwon Kook-Hwan
Elms Richard
Le Toan
MacPherson Kwok & Chen & Heid LLP
ProMOS Technologies Pte. Ltd.
Shenker Michael
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