Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
2001-03-30
2004-09-14
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C710S266000, C710S014000, C713S500000, C361S778000
Reexamination Certificate
active
06792489
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of integrated circuit devices. More particularly, the invention relates to multistage configuration and power setting for processor chips.
2. Background Information
In a computer system, configuration signals, such as those that define voltage and bus clock frequency needed for proper operation of the system's processor, are set by hard wiring a set of pins located on the processor package or by providing a resistor pull up/down stuffing option. This means that when a configuration signal changes, the processor package has to change or the Bill of Materials and resistor population must change, respectively.
For example, designers typically develop and use a new package for each combination of configuration signals for a given processor. Having a new processor package for each combination of configuration signals is not desirable especially considering that configuration signals typically change several times during the processor's lifetime. If there are three different operating frequencies for a particular processor, engineers design three different processor packages to accommodate the three frequencies. Similarly, if there are three different operating voltages for a particular processor, engineers design three different processor packages to accommodate the three voltages. If there were three operating frequencies and three operating voltages for a particular processor, there would be nine different processor packages.
Having more than one package for a particular processor merely because a voltage or frequency changes generally causes logistics issues to arise during manufacturing of processor packages. There may be delays due to lead-time of the new package, for example. Having more than one package for a particular processor also generates a significant cost overhead. Not only do new packages have to be designed, but the new packages have to be maintained in inventory and be quality assured. This can be burdensome, time consuming, and uneconomical.
Using a resistor stuffing option, results in liability problems and possible reliability problems resulting from illegal alteration to the stuffing configuration. Processor re-markers may alter the configuration stuffing options to increase operational frequency and stability in order to illegally resell the product as a higher performance product than it was designed for. This may lead to reduced product reliability and inherent stability problems resulting from operating the part out of specifications.
Another approach beginning to be implemented is the use of a “Dynamic Processor Configuration and Power-up” circuit, as described in U.S. Ser. No. 09/746,168 to Sarangi et al., where the platform power planes must sequence properly to ensure the configurations signals, driven by fuses on the die, are valid. The power sequencing can result in added cost and complexity to the design. Additionally, the settings are static and cannot be changed during operation
REFERENCES:
patent: 5630090 (1997-05-01), Keehn et al.
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patent: 6059191 (2000-05-01), Sedlak et al.
patent: 6385735 (2002-05-01), Wilson et al.
patent: 6433405 (2002-08-01), Gunderson et al.
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patent: 6449170 (2002-09-01), Nguyen et al.
Osburn Edward P.
Sarangi Ananda
Taylor Gregory F.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vo Tim
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