Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-08-16
2003-05-13
Phu, Phuong (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S232000
Reexamination Certificate
active
06563897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a symbol timing recovery circuit, for recovering the symbol timing of a received signal and, more particularly, to a multirate symbol timing recovery circuit capable of accommodating differing symbol rates, and to a recording medium having a program recorded thereon for enabling a computer to design the same.
2. Description of the Related Art
Several methods are practiced to recover timing for discriminating symbols contained in a received signal (symbol timing); for example, in one method, symbol frequency components are extracted from the received signal; and in another, the timing of the symbol discrimination clock is controlled so as to synchronize it to the symbol timing of the received signal.
In Japanese Unexamined Patent Publication No. 4-104542, there is proposed a technique that lends itself to digital implementation and that, if implemented digitally, is capable of processing high-speed signals; this technique, as opposed to the above-described method, controls the symbol timing of the received signal so as to synchronize it to a fixed-frequency clock by controlling the tap coefficients-of a finite impulse response (FIR) filter through which the received signal is passed.
This technique of synchronizing the symbol timing of the received signal to a fixed clock uses a clock frequency (sampling frequency) higher than twice the symbol rate of the received signal. Here, the sampling frequency must be chosen to fall within capture range. That is, the sampling frequency must be set at twice the symbol rate (or an integral multiple thereof).
Therefore, if the symbol rate of the input signal changes, the sampling frequency must also be changed correspondingly. If the symbol rate of the input signal changes by an n-th submultiple of the fundamental frequency, the change can be accommodated by changing the divide-by ratio in the frequency divider. However, if signals of symbol rates of 5 Mbauds and 3.4 Mbauds, for example, are both to be accommodated, the necessary sampling frequency cannot be generated by a simple divide-by operation, but external circuitry such as a crystal oscillator must be changed or a complex frequency dividing circuit-must be provided.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a multirate symbol timing recovery circuit capable of accommodating differing symbol rates without having to provide a complex frequency dividing circuit or to change external circuitry. It is another object of the invention to provide a recording medium having a program recorded thereon for enabling a computer to design such a timing recovery circuit.
According to the present invention, there is provided a multirate symbol timing recovery circuit comprising: a frequency divider for frequency-dividing a first clock to produce a second clock; a finite impulse response filter for computing, from the value of an input signal at the timing of the second clock, values at a zero-crossing point and a data discrimination point of the input signal at the timing of the second clock by using supplied tap coefficients, and for outputting the computed values, thereby shifting the phase of the zero-crossing point and the data discrimination point of the input signal so as to match the timing of the second clock; a phase comparator for detecting a phase error occurring at the zero-crossing point appearing at an output of the finite impulse response filter; a loop filter for passing therethrough low-frequency components contained in an output of the phase comparator; an adder for adding a prescribed value to an output of the loop filter; an oscillator for outputting a signal whose frequency varies with a value output from the adder; and a tap coefficient determining device for determining the tap coefficients based on an output of the oscillator, and for supplying the tap coefficients to the finite impulse response filter.
According to the present invention, there is also provided a recording medium having a program recorded thereon for enabling a computer to design a multirate symbol timing recovery circuit comprising: a frequency divider for frequency-dividing a first clock to produce a second clock; a finite impulse response filter for computing, from the value of an input signal at the timing of the second clock, values at a zero-crossing point and a data discrimination point of the input signal at the timing of the second clock by using supplied tap coefficients, and for outputting the computed values, thereby shifting the phase of the zero-crossing point and the data discrimination point of the input signal so as to match the timing of the second clock; a phase comparator for detecting a phase error occurring at the zero-crossing point appearing at an output of the finite impulse response filter; a loop filter for passing therethrough low-frequency components contained in an output of the phase comparator; an adder for adding a prescribed value to an output of the loop filter; an oscillator for outputting a signal whose frequency varies with a value output from the adder; and a tap coefficient determining device for determining the tap coefficients based on an output of the oscillator, and for supplying the tap coefficients to the finite impulse response filter.
REFERENCES:
patent: 4906941 (1990-03-01), Kato et al.
patent: 5570390 (1996-10-01), Kaku et al.
patent: 6236263 (2001-05-01), Iwamatsu
patent: 6249557 (2001-06-01), Takatori et al.
patent: 6314145 (2001-11-01), van Driest
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Phu Phuong
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