Multipurpose graded silicon oxynitride cap layer

Details Multipurpose graded silicon oxynitride cap layer Multipurpose graded silicon oxynitride cap layer

2000-05-10

2001-10-23

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S592000, C438S593000, C438S655000, C438S584000, C257S576000, C257S750000

Reexamination Certificate

active

06306758

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements associated with a multipurpose graded silicon oxynitride cap layer in non-volatile memory semiconductor devices.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell
8
is depicted in
FIG. 1
a
. As shown, memory cell
8
is viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and within which a source
13
a
and a drain
13
b
have been formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polysilicon.
On top of control gate
26
is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional chemical vapor deposition processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a
. When programmed, floating gate
16
will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate
16
does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge is removed from floating gate
16
by way of the erasure voltage applied to source
13
a.
FIG. 1
b
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in
FIG. 1
a
). In
FIG. 1
b
, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1
b
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a. Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b
. Floating gates
16
a
,
16
b
, and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a-b
. Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a-c
and field oxides
14
a-b
. Interpoly dielectric layer
24
isolates floating gates
16
a-c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of
FIGS. 1
a-b
, places a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells. Of particular concern is the need to control the deposition and patterning processes associated with the layer stack. As such, there is a need to provide a layer stack that is relatively easy to control during deposition and etching, readily adaptable to reduced-size critical dimensions, and cost effective.
SUMMARY OF THE INVENTION
These needs and others are met by the present invention, which provides methods and arrangements that provide a layer stack that is not only cost effective, but more importantly controllable during deposition and etching, and advantageously adaptable to reduced-size critical dimension semiconductor devices.
In accordance with one aspect of the present invention, a graded silicon oxynitride cap layer is employed to reduce the overall thickness or height of the layer stack. The graded silicon oxynitride cap layer is configured to increase process control during patterning of the layer stack and can provide multiple functions. By way of example, in accordance with certain aspects of the present invention, a graded silicon oxynitride cap layer serves as: (1) a cap layer to prevent an underlying silicide layer from lifting; (2) a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes; (3) a stop layer to prevent over-etching during subsequent source patterning processes; and/or, (4) an anti-reflective coating (ARC) to improve the resolution associated with the subsequent contact patterning processes.
Thus, in accordance with certain embodiments of the present invention, a cap layer is provided for use in a semiconductor device. The cap layer includes a layer of silicon oxynitride having within it a first region and at least one second region. The first region has a first concentration of nitrogen and the second region has a second concentration of nitrogen, which is lower than the first concentration of nitrogen in the first region. By way of example, in certain other embodiments, the first concentration of nitrogen is at least about 10 atomic percent, and/or the second concentration of nitrogen is between about 2 to about 3 atomic percent. In accordance with still other embodiments of the present invention, the first concentration of nitrogen varies within the first region, and/or the second concentration of nitrogen varies within the second region. By way of example, in certain embodiments, the first and second concentrations of nitrogen are based on at least one mathematical function with respect to the thickness of the layer of silicon oxynitride. By way of example, the mathematical function can include a linear function, a non-linear function, and/or a step function.
The above stated needs and others are met by a semiconductor device provided in accordance with certain other embodiments of the present invention. The semiconductor device includes a substrate, and a layer stack formed on the substrate. The layer sta

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