Multiprocessor write-into-cache system incorporating...

Details Multiprocessor write-into-cache system incorporating... Multiprocessor write-into-cache system incorporating...

2005-12-06

2005-12-06

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S121000, C711S152000

Reexamination Certificate

active

06973539

ABSTRACT:
A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common code/data set shared by processes running in the processors by imposing first delays on all other processors in the system while, at the same time, mitigating any adverse effect on performance of processors attempting to access a gateword other than the first gateword. This is achieved by starting a second delay in any processor which is seeking ownership of a gateword other than the first gateword and truncating the first delay in all such processors by subtracting the elapsed time indicated by the second delay from the elapsed time indicated by the first delay.

REFERENCES:
patent: 6314499 (2001-11-01), Kermani
patent: 6401176 (2002-06-01), Fadavi-Ardekani et al.
patent: 6551084 (2003-04-01), Sundstrom
patent: 6587926 (2003-07-01), Arimilli et al.

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