Multiprocessor with split transaction bus architecture providing

Details Multiprocessor with split transaction bus architecture providing Multiprocessor with split transaction bus architecture providing

1998-03-09

2000-02-29

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711146, G06F 1300

Patent

active

060322314

ABSTRACT:
A method and system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase. The bus modules are arranged for access by a prescribed resource stage to facilitate "RETRY" operations. The method includes providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access. The system provides components supporting the above method steps.

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