Multiprocessor system with partial broadcast capability of a cac

Details Multiprocessor system with partial broadcast capability of a cac Multiprocessor system with partial broadcast capability of a cac

1997-03-19

2000-03-14

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711148, 711146, G06F 1212

Patent

active

060386444

ABSTRACT:
Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The destinations of a coherent processing request which should be sent to other processor units are limited by the information stored in this table. The interconnection network broadcasts the request to the limited destinations. When the processor unit of the destination of this processing request sends back a cache status of the data designated by the request, it also sends back the caching status in the processor unit concerning a specific memory area which includes the data. Depending on this send back, the request source processor unit renews a portion relating to the destination processor unit within the caching status concerning that specific memory area stored in the processor unit.

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L. Censier & P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems", IEEE Transactions on Computers, Dec. 1978, vol. C-27, No. 12, pp. 1112-1118.

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