Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-08-14
1998-09-01
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711100, 711118, 711121, 711144, 711154, G06F 1200, G06F 1300
Patent
active
058025707
ABSTRACT:
Data sets of sequential data strings at a particular point in time are assigned to processing elements of a multiprocessor system at high speed and processing is executed efficiently in parallel. A mechanism for preventing allocation due to all-read to a cache block which has not yet been referred from another cache is added by providing a reference bit with respect to cache blocks. The reference bit becomes 0 when new data is read to the cache block and becomes 1 when the cache block is referenced by a CPU. In the case of reading data from another cache, if a block corresponding thereto can be replaced without the need to be written back to the other cache and the reference bit is 1, data is fetched to the shared cache memory.
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Kawase Kei
Moriyama Takao
Henkler Richard A.
International Business Machines Corp.
Swann Tod R.
Thai Tuan V.
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