Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-07-18
2006-07-18
Vital, Pierre M. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000
Reexamination Certificate
active
07080215
ABSTRACT:
The present invention provides a multiprocessor which can decrease a required waiting time of access to improve the processing time thereof. There is provided a multiprocessor apparatus having a plurality of processor units in which each of processor units is arranged to include a processor, a local memory unit utilized for storing therein a copy of the whole data of a shared memory, and a copy circuit for controlling the local memory unit in the update processing when the contents of the shared memory are updated by the processor unit, wherein when the processor requests a piece of data that shall be stored in the shared memory with a data reading command, then the local memory unit reads the corresponding piece of data from the copied data stored therein and supplies it to the processor. The apparatus is applicable to a multiprocessing of a real time system, for example.
REFERENCES:
patent: 5353428 (1994-10-01), Shibata
patent: 5615334 (1997-03-01), Wang et al.
patent: 60-183652 (1985-09-01), None
patent: 01-297759 (1989-11-01), None
patent: 06-208547 (1994-07-01), None
patent: 8-30510 (1996-02-01), None
patent: 09-044399 (1997-02-01), None
Notice of Rejection dated Feb. 10, 2006.
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