Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2011-05-17
2011-05-17
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S119000, C711S122000, C711S163000, C711S165000
Reexamination Certificate
active
07945754
ABSTRACT:
A multiprocessor system includes processors each having a primary cache and a secondary cache shared by the processors. The processors each include a read unit that reads data from the primary cache, a request unit that makes a write request when the data to be read is not stored in the primary cache, a measuring unit that measures an elapsed time since the write request is made, a receiving unit that receives a read command from an external device, a comparing unit that compares specific information for specifying data, for which the read command has been received, with specific information for specifying data, for which the write request has been made, and a controller that suspends reading of the data according to the read command, when pieces of specific information are the same, and the elapsed time measured is less than a predetermined time.
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Fujitsu Limited
Lane Jack A
Staas & Halsey , LLP
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