Multiprocessor system having distinct data bus and address bus a

Details Multiprocessor system having distinct data bus and address bus a Multiprocessor system having distinct data bus and address bus a

1997-05-23

2000-06-20

Peikari, B. James

Electrical computers and digital data processing systems: input/

Access arbitrating

710241, 710242, 710113, 710119, G06F 1336

Patent

active

060789832

ABSTRACT:
A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

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