Multiprocessor system for maintaining cache coherency by checkin

Details Multiprocessor system for maintaining cache coherency by checkin Multiprocessor system for maintaining cache coherency by checkin

1994-02-24

1996-06-25

An, Meng-Ai

Boots, shoes, and leggings

395446, 395448, 395403, 3642283, 3642292, 3642384, 3642401, 3642434, 36424344, 364264, 3642644, 3642647, 364DIG1, G06F 1206

Patent

active

055309330

ABSTRACT:
A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

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Litaize, et al., "Multiprocessors With A Serial Multiport Memory & A Pseudo Crossbar of Serial Links Used as Processor-Memory Switch", Dec. 1, 1989, Computer Architecture News, vol. 17, No. 6, pp. 8-21.

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