Multiprocessor system bus with a data-less castout mechanism

Details Multiprocessor system bus with a data-less castout mechanism Multiprocessor system bus with a data-less castout mechanism

1999-11-09

2001-08-28

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S143000, C711S144000, C711S145000, C711S146000

Reexamination Certificate

active

06282615

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to cache memories in general and, in particular, to a method and apparatus for casting out data from a cache memory within a data processing system. Still more particularly, the present invention relates to a method and apparatus for casting out data within a cache memory hierarchy for a multiprocessor data processing system.
2. Description of the Prior Art
In a symmetric multiprocessor (SMP) data processing system, all of the processing units are generally identical; that is, they all utilize a common set or subset of instructions and protocols to operate and, generally, have the same architecture. Each processing unit includes a processor core having multiple registers and execution units for carrying out program instructions. Each processing unit may also have a multi-level cache memory hierarchy.
A multi-level cache memory hierarchy is a cache memory system consisting of several levels of cache memories, each level having a different size and speed. Typically, the first level cache memory, commonly known as the level one (L
1
) cache, has the fastest access time and the highest cost per bit. The remaining levels of cache memories, such as level two (L
2
) caches, level three (L
3
) caches, etc., have a relatively slower access time, but also a relatively lower cost per bit. Typically, each lower cache memory level has a progressively slower access time and a lower per-bit cost.
Because there are many possible operating scenarios in which data can be transferred between cache memory hierarchies, and between cache levels within a cache memory hierarchy in a multiprocessor data processing system, it is important to efficiently transfer data from one cache to another. The present disclosure is related to a method and apparatus for casting out data within a cache memory hierarchy of a multiprocessor data processing system. Data may be casted out from one cache to another cache, typically a lower level cache, for data deallocation or other reasons.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5623633 (1997-04-01), Zeller et al.
patent: 5761725 (1998-06-01), Zeller et al.

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