Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
1999-05-13
2002-01-15
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S107000, C710S109000, C710S111000, C710S113000, C710S114000, C710S115000, C709S208000, C709S211000, C709S213000, C709S214000, C712S011000, C712S015000, C712S025000, C712S028000, C712S032000, C712S033000
Reexamination Certificate
active
06339807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiprocessor system having a plurality of processor elements commonly using a single bus and a bus arbitrating method for determining a priority of utilizing the bus of the multiprocessor system.
2. Description of the Related Art
The multiprocessor system shown in
FIG. 7
is a multiprocessor system having a single bus. In this system, since only a single communication can be carried out at one time, a selecting mechanism, for example, an arbitrating circuit for selecting only one processor element (PE) to use the bus
10
is necessary. Further, to use the bus more effectively, a method for assigning the priority dynamically rather than assigning constant priority to each processor element during the arbitrating is introduced. In this case, for example, the bus assignment by a priority level is effective.
So far, there are two types of arbitrating circuits, the concentration type and the distribution type. A concentration type arbitration circuit, as shown in
FIG. 8
, for example, is constituted by a plurality of processor elements
12
,
22
,
32
and an arbitrator
40
.
In the concentration type arbitrating circuit, bus request signals are sent by the processor elements request the utilization of the bus directly or indirectly to the arbitrator
40
, and then a permission signal from the arbitrator
40
is returned to the processor element that is permitted to use the bus: That is, in a concentration type arbitrating circuit, after three processes of sending a bus request signal by a processor element, selecting a processor element by the arbitrator and transmitting a permission signal from the arbitrator, the processor element requiring to use the bus is first permitted to use the bus.
An example of a distribution type arbitrating circuit is shown in FIG.
9
. As illustrated, the distribution type arbitrating circuit is constituted by a plurality of processor elements
12
,
22
,
32
connected to the bus
10
. Further, arbitrators
11
,
21
,
31
for arbitrating priorities of utilizing the bus is provided to each processor element.
In the distribution type arbitrating circuit illustrated in
FIG. 9
, permission signals can be generated in a plurality of places (usually by arbitrators of each processor element). In the arbitrating circuit, for the purpose of arbitrating according to the priority levels, each arbitrator needs to hold the priority levels of every processor element. Further, if the priority level of a single processor element is changed, it is necessary to notify the changing to every processor element.
By this kind of distribution type arbitrating circuit, since a processor element can judge directly whether the bus is available or not by the arbitrator provided to it and the bus using is permitted according to the result of the judgment, the time needed from the sending of the bus request signal to the receiving of the bus utilizing permission can be shortened compared with the concentration type of bus arbitrating circuit.
But in the multiprocessor system of the prior art mentioned above, there are demerits of the concentration type and distribution type bus arbitrating circuits, respectively. For example, in a multiprocessor system having a concentration type arbitrating circuit, three processes of sending a bus request signal from a processor element, selecting a processor element by an arbitrator and sending a bus permission signal from the arbitrator are essential. Further, since these three processes which can not be performed simultaneously have to be processed one by one, the time needed for the arbitrating becomes longer.
On the other hand, in a multiprocessor system having a distribution type arbitrating circuit, the arbitration taking use of the priority level is carried out, the arbitrators provided to every processor element have to store the priority levels of every processor element. Further, when the priority level of a single processor element is changed notification to every processor element about the change is necessary. Thus capacity of communication of the whole system must become larger. Furthermore, since each arbitrating circuit has a circuit for selecting processor elements, the scale of each arbitrating circuit becomes larger when a complicated selecting method is utilized hence there is a disadvantage that the scale of the whole system becomes larger.
SUMMARY OF THE INVENTION
The present invention was made in consideration of such a circumstance and has as an object thereof to provide a multiprocessor system and a bus arbitrating method of the same for realizing a system of high speed, shortening the time of bus arbitration without a large increase of the circuit scale.
To achieve the above object, according to an aspect of the present invention, there is provided a multiprocessor system having a plurality of processor elements operating independently and transmitting information through a common bus, comprising: a request value generator generating a bus request value according to a priority level of the processor element when the processor element requests the utilization of the common bus, a transmitter transmitting a bus request signal and the bus request value to the bus when the processor element requests the utilization of the bus, a controlling circuit judging the priority of utilizing the bus according to utilizing situation of the common bus and the bus request value of the processor element transmitting the bus request signal when the processor element transmitted the bus request signal, and a bus arbitrating circuit connected to the bus determining a processor element to utilize the common bus according to the utilizing situation of the bus and the priority levels of the processor elements transmitting bus request signals to the common bus in cases when there is a plurality of processor elements transmitting the bus request signals to the common bus and the controlling circuit can not determine a processor element having priority of utilizing the bus.
Preferably, in the present invention, the request value generator, the transmitting and the controlling circuit are provided to each processor element corresponding to each processor element. Further, there is provided a memory to each processor element storing a priority level data of M (M≧0, an integer) bits indicating the priority level of the processor element.
Preferably, in the present invention, the request value generator generates the bus request value with at least upper m (m≦M, an integer) bits of the priority level data stored in the memory, and the bit width of the bus is at least of m×N bits in case that there is N (N≧2, an integer) number of the processor elements connected to the bus.
Preferably, in the present invention, the priority level data of each processor element is variable, and the controlling circuit rewriting the priority level data is in the memory.
Further, according to anther aspect of the present invention, there is provided a method for determining a priority of utilizing a bus for a plurality of processor elements connected to a single bus, said method comprising the steps of: providing a controlling circuit judging the priority of utilizing the bus to each processor element, transmitting a bus request value to the bus according to a bus request signal from the processor element that requests the utilization of the bus and a priority level of the processor element, determining the priority of utilizing the bus for the processor element according to utilizing situation of the bus and the bus request value from the processor element by the controlling circuit provided to the processor element, providing a common bus arbitrating circuit to the bus, and determining a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements transmitting the bus request signals to the bus by the bus arbitrating circuit in case when the bus request signals from a plurality of the
Dharia Rupal
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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