Multiprocessor system and method to maintain cache coherence

Details Multiprocessor system and method to maintain cache coherence Multiprocessor system and method to maintain cache coherence

2004-06-23

2008-08-26

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S120000, C711S133000, C711S145000, C710S260000

Reexamination Certificate

active

07418555

ABSTRACT:
A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the multiprocessor system receives an access request for a data block of the memory unit from one processor. The processors may also include a processing unit. When the processor shares a data block, the processing unit may invalidate the shared data block in the cache memory, write the shared data block from the write buffer to a memory unit, and forward an interrupt completion response to a control unit.

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