Multiprocessor system and method for simultaneously placing...

Details Multiprocessor system and method for simultaneously placing... Multiprocessor system and method for simultaneously placing...

2005-02-15

2005-02-15

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

06857084

ABSTRACT:
Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode.

REFERENCES:
patent: 6031991 (2000-02-01), Hirayama
patent: 6718294 (2004-04-01), Bortfeld
MIPS Technologies MIPS32 4K tm Processor Core Family Integrator's Manual. Doc. No. MD00036 Rev. 1.08 26-2001—Author(s)—MIPS Tech. Inc.
“MIPS32 4KEc tm Processor Core Datasheet”—Author(s)—MIPS Tech. Inc.

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