Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-03-08
2011-03-08
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S144000, C711SE12033
Reexamination Certificate
active
07904665
ABSTRACT:
The multiprocessor system includes multiple cells having identical functions, and each of the multiple cells has a processor, a cache memory, and a main memory. The multiple cells include the first cell as a request cell, the second cell as a home cell, and the third cell as an owner cell. The latest version of the target data stored in the main memory of the second cell is stored in the cache memory of the third cell. When the first cell issues a read request for the target data to the second cell, the second cell issues a snoop request to the third cell in response to the read request. The third cell directly transmits the target data to the first cell in response to the snoop request. Also, the third cell issues the reply write back to the second cell in response to the snoop request. The first cell issues a request write back to the same address as that of the target data in the second cell. The second cell discards the reply write back when the reply write back from the third cell is received later than the request write back from the first cell.
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Japanese Office Action dated May 27, 2010 with English translation thereof.
Bernard Daniel J
Bragdon Reginald G
McGinn IP Law Group PLLC
NEC Computer Techno, Ltd.
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