Multiprocessor system and failure recovering system

Details Multiprocessor system and failure recovering system Multiprocessor system and failure recovering system

2010-03-29

2011-11-01

Riad, Amine (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

08051325

ABSTRACT:
A multiprocessor system includes a plurality of nodes, each of which includes a plurality of processors, a plurality of memories, and first and second node controllers. Unique identifiers are assigned to all the components. Each of the first and second node controllers includes: each of first and second request control sections configured to determine the identifier of a transmission destination of a request based on a memory address of an access destination of the request; each of first and second registers configured to hold in the first request control section, the identifier of the transmission destination of the request; a first routing table configured to specify one of the first request control section and the second request control section as an output destination of the request based on the identifier held by the first register, the identifier held by the second register, the identifier of the transmission destination of the request, when receiving the request, and a second routing table configured to specify a signal line for the identifier of the transmission destination of the request based on the identifier of the transmission destination which is determined by the first request control section or the second request control section, to transmit the request.

REFERENCES:
patent: 7236453 (2007-06-01), Visser et al.
patent: 7493432 (2009-02-01), Fukazawa et al.
patent: 7769921 (2010-08-01), Hirayama
patent: 2001/0037475 (2001-11-01), Bradshaw et al.
patent: 2009/0287955 (2009-11-01), Matsumoto et al.

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