Multiprocessor system

Electrical computers and digital data processing systems: input/ – Interrupt processing – Source or destination identifier

Reexamination Certificate

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Reexamination Certificate

active

08051234

ABSTRACT:
The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.

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Japanese Office Action, with partial English translation, issued in Japanese Patent Application No. 2007-006621, issued Mar. 24, 2011.

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