Multiprocessor system

Details Multiprocessor system Multiprocessor system

2007-01-02

2007-01-02

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S142000, C711S143000

Reexamination Certificate

active

10886036

ABSTRACT:
A splittable/connectible bus140and a network1000for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory160and a group setup register170for storing bus-splitting information are provided in a directory control circuit150that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network.Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

REFERENCES:
patent: 6088770 (2000-07-01), Tarui et al.
Daniel Lenoski et al., “The Stanford Dash Multiprocessor”, Mar. 1992 IEEE, pp. 63-79.

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