Multiprocessor interrupt handling system and method

Details Multiprocessor interrupt handling system and method Multiprocessor interrupt handling system and method

2005-10-04

2005-10-04

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S269000, C710S048000

Reexamination Certificate

active

06952749

ABSTRACT:
An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level. The interrupt handling system also permits software based interrupts wherein, for example, one processor may interrupt another processor.

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patent: 5297290 (1994-03-01), Masui et al.
patent: 5590380 (1996-12-01), Yamada et al.
patent: 6070221 (2000-05-01), Nakamura

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