Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-28
2006-02-28
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C712S010000, C712S028000, C712S029000, C370S439000
Reexamination Certificate
active
07007128
ABSTRACT:
A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.
REFERENCES:
patent: 3308436 (1967-03-01), Borck, Jr. et al.
patent: 4402045 (1983-08-01), Krol
patent: 5097412 (1992-03-01), Orimo et al.
patent: 5179715 (1993-01-01), Andoh et al.
patent: 5504918 (1996-04-01), Collette et al.
patent: 5606686 (1997-02-01), Tarui et al.
patent: 5671430 (1997-09-01), Gunzinger
patent: 5918249 (1999-06-01), Cox et al.
patent: 6178466 (2001-01-01), Gilbertson et al.
patent: 6246692 (2001-06-01), Dai et al.
patent: 6421775 (2002-07-01), Brock et al.
patent: 6519649 (2003-02-01), Arimilli et al.
patent: 6519665 (2003-02-01), Arimilli et al.
patent: 6526467 (2003-02-01), Joh
patent: 6529999 (2003-03-01), Keller et al.
patent: 6591307 (2003-07-01), Arimilli et al.
patent: 6728841 (2004-04-01), Keller
patent: 6820158 (2004-11-01), Lee et al.
patent: 6848003 (2005-01-01), Arimilli et al.
patent: 6901491 (2005-05-01), Kohn et al.
patent: 2004/0088523 (2004-05-01), Kessler et al.
patent: 2004/0117510 (2004-06-01), Arimilli et al.
patent: 2005/0021699 (2005-01-01), Kota et al.
patent: 2005/0060473 (2005-03-01), Duncan et al.
patent: 2005/0091473 (2005-04-01), Aguilar et al.
“Omega-Crossbar Network,” Oct. 1, 1984, IBM technical Disclosure Bulletin, vol. 27, No. 5, p. 2811-2816.
Arimilli Ravi Kumar
Chung Vicente Enrique
Joyner Jody Bern
Lewis Jerry Don
Auve Glenn A.
Dillon & Yudell LLP
Mason Donna K.
Salys Casimer K.
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