Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-03-31
2001-08-28
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Reexamination Certificate
active
06282601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and in particular to interrupt handling within a multiprocessor data processing system. Still more particularly, the present invention relates to a multiprocessor data processing system and method of interrupt handling that facilitate identification of a processor requesting a System Management Interrupt (SMI).
2. Description of the Related Art
In a conventional computer system, the occurrence of certain events causes a hardware component of the computer system to assert an interrupt signal. The assertion of an interrupt signal triggers some response by the computer system, typically the execution of an interrupt handler that calls an appropriate interrupt vector for the event. Events whose occurrence may trigger an interrupt generally include the receipt of peripheral input (e.g., from a mouse or keyboard), a power management timer indicating that a user input has not been received in a threshold amount of time, the execution of a software interrupt command, etc.
The differences in the types of events triggering assertion of the interrupt signals and the differing importance of the events has led to the classification of interrupts into various categories. For example, the receipt of peripheral inputs typically triggers “normal” interrupts having various assigned priorities. The highest priority events, such as a severe memory error or detection of impending power failure, trigger non-maskable interrupts (NMIs), so called because a processor cannot defer handling of the interrupt by masking (i.e., blocking) interrupts of that priority. Another classification of interrupts is System Management Interrupts (SMIs), which denote interrupts, such as those generated by Advanced Power Management (APM) controllers, that affect the maintenance, configuration, and operation of the computer system itself rather than merely software executed by the computer system.
In a conventional multiprocessor computer system, an SMI generated by a processor is received by an interrupt controller or other interrupt handling hardware, which routes the SMI to a designated processor for handling. In response to assertion of its SMI line, the handling processor suspends execution of its current thread and executes an SMI handler that services the SMI. Typically, some or all of the other processors will similarly suspend execution in response to the SMI and save the states of their respective threads. The SMI handler then examines the instruction sequence within the saved state of each processor in turn to determine which processor issued the SMI request. In order to expedite identification of the requesting processor, conventional SMI handlers typically examine only the last instruction executed by each processor in order to locate an SMI-generating instruction. Thus, in order to accommodate this SMI handler behavior, the hardware design of the interrupt hardware must ensure that the SMI is generated and recognized by each processor before each processor executes the next instruction within its respective thread.
The present invention recognizes that this condition is more difficult to satisfy as processor clock rates increase. The present invention therefore provides an improved multiprocessor data processing system and method for handling interrupts in which the identification of the processor requesting an SMI is can be readily determined without having to satisfy such severe interrupt timing constraints.
SUMMARY OF THE INVENTION
In accordance with the present invention, a request for a system management interrupt by a requesting processor within a multiprocessor data processing system causes the state of at least the requesting processor to be saved in memory. Each processor's saved state includes contents of at least one internal software-writable register, where the software-writable register of the requesting processor contains an identifying signature. A system management interrupt handler is then executed. Execution of the system management interrupt handler entails determining, from the contents of at least one internal software-writable register saved within memory, the identity of the requesting processor. The system management interrupt handler then handles the system management interrupt in accordance with the determination of the requesting processor. The handling of the system management interrupt may entail reading data from or writing data into the saved state of the requesting processor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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patent: 5603038 (1997-02-01), Crump et al.
patent: 6145048 (2000-11-01), Klein
patent: 6192442 (2001-02-01), Haren et al.
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Goodman Steven Dale
Khatri Bharat B.
Beausoleil Robert
Bracewell & Patterson LLP
Chung-Trans X.
International Business Machines - Corporation
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