Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-08-09
2011-08-09
Elmore, Reba I (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C711S167000
Reexamination Certificate
active
07996629
ABSTRACT:
Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, and a set of controller/translator units TX1, TX2, TX3arranged to convert respective application programs into program threads T1, T2, etc., which are executed by the processors. Each controller/translator unit sets a first mode where a single thread T1executes on a single processor P1, orders a second mode for two or more threads T1, T2that are forced to execute one at a time on a single processor P2such as by setting affinity with that processor, and orders a third mode to selectively apply active memory consistency protection in relation to accesses to explicit or implicit shared memory while allowing the multiple threads T1, T2, T3, T4to execute on the multiple processors.
REFERENCES:
patent: 5890189 (1999-03-01), Nozue et al.
patent: 2009/0198938 (2009-08-01), Arimilli et al.
Dankel Gisle
Wan Kit M.
Elmore Reba I
International Business Machines - Corporation
Talpis Matthew B.
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