Multiprocessor computing apparatus with optional coherency direc

Details Multiprocessor computing apparatus with optional coherency direc Multiprocessor computing apparatus with optional coherency direc

1997-12-12

2000-01-04

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

714 5, G06F 1208

Patent

active

060121270

ABSTRACT:
A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.

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patent: 5446863 (1995-08-01), Stevens et al.
patent: 5604882 (1997-02-01), Hoover et al.
patent: 5608878 (1997-03-01), Arimilli et al.

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