Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1997-08-29
2001-09-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S203000, C711S209000
Reexamination Certificate
active
06295584
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a computer system with multiple processors located on a plurality of nodes. More particularly, this invention relates to using memory map translation to uniquely address memory space on such a multiprocessor computer system.
BACKGROUND OF THE INVENTION
Multiprocessor computers by definition contain multiple processors that can execute multiple parts of a computer program or multiple programs simultaneously. In general, this parallel computer executes computer programs faster than conventional single processor computers, such as personal computers (PCs), that execute the parts of a program sequentially. The actual performance advantage is a function of a number of factors, including the degree to which parts of a program can be executed in parallel and the architecture of the particular multiprocessor computer at hand.
Multiprocessor computers may be classified by how they share information among the processors. Shared-memory multiprocessor computers offer a common physical memory address space that all processors can access. Processes within a program communicate through shared variables in memory that allow them to read or write to the same memory location in the computer. Message passing multiprocessor computers, on the other hand, have a separate memory space for each processor. Processes communicate through messages to each other.
Multiprocessor computers may also be classified by how the memory is physically organized. In distributed shared-memory computers, the memory is divided into modules physically placed near each processor. Although all of the memory modules are globally accessible, a processor can access memory placed nearby faster than memory placed remotely. Because the memory access time differs based on memory location, distributed shared-memory systems are often called non-uniform memory access (NUMA) machines. By contrast, in centralized shared-memory computers, the memory is physically in just one location. Such centralized shared-memory computers are called uniform memory access (UMA) machines because the memory is equidistant in time and space from each of the processors. Both forms of memory organization typically use high-speed cache memory in conjunction with main memory to reduce execution time.
Multiprocessor computers with distributed shared memory are often organized into multiple nodes with one or more processors per node. The nodes interface with each other through a network by using a protocol, such as the protocol described in the Scalable Coherent Interface (SCI)(IEEE 1596). Companies, like Intel Corporation, have developed “chip sets” which may be located on each node to provide memory and I/O buses for the multiprocessor computers.
Such chip sets often have predetermined memory addresses for basic input/output systems (BIOS), interrupts, etc. For example, a chip set following an Industry Standard Architecture (ISA) has memory addresses dedicated to particular functions, such as system BIOS, video BIOS, graphics adapters, expansion memory, etc. This memory area, often called the ISA space, extends between addresses 640 KB to 1 MB for typical PC-based environments. A chip set may also include an interrupt controller that has a fixed range of addresses. An example of an interrupt controller is the Advanced Programmable Interrupt Controller (APIC) developed by Intel Corporation. The interrupt controller also has a fixed range of memory addresses, often called interrupt controller (IC) space.
In a multinode computer system, each node contains its own chip set to interface with its local bus. Consequently, memory addresses between nodes overlap with each other. For example, two or more nodes may have their own ISA space addressed between 640 KB to 1 MB. By contrast, single-node computer systems only have one chip set and each memory address in the system is unique.
Typically, in either the single-node or multinode computer system, a single operating system controls the computer system (some systems may contain more than one operating system). The operating system includes a program (often called a kernel) that performs a number of tasks central to the computer's operation including managing memory, files and peripheral devices, launching application programs, and allocating system resources.
Recently developed operating systems (e.g., Windows NT) are designed for single-node multiprocessor environments and expect each memory address in the system to be unique. For this reason, such operating systems cannot run on a multinode computer system where memory addresses between nodes overlap due to the requirements of the chip sets. For example, in a multinode environment, a processor on one node cannot access ISA space on another node without a mechanism designed to allow for this.
An objective of the invention, therefore, is to provide a shared-memory, multinode computer system utilizing chip sets developed for single-node computer systems. A further objective is to provide such a system that allows an operating system to access all system resources from any processor within the system. Still a further objective is to provide such a system that can use the well-established PC-based BIOS for initialization.
SUMMARY OF THE INVENTION
The present invention provides a multiprocessor computer system with a distributed shared memory that has the advantages of a multinode environment (e.g., increased speed and reduced local bus traffic), but with the characteristics of a single-node environment. Thus, operating systems designed for single-node environments can be used to run the multinode environment. The invention also takes advantage of standard hardware and software used in the well-developed, PC-based computers, such as commercially used chip sets and BIOS.
In one aspect of the invention, a memory map having the appearance of a single-node environment is used to uniquely identify the memory locations in the computer system. For memory locations that have overlapping addresses between nodes, the memory locations are assigned representative address locations. When an operating system or other program accesses a representative address, the computer system ascertains or determines which node is associated with the request and sends the request to that node. The address sent with the request is then translated to a local address for that node. Thus, overlapping address spaces on nodes can be uniquely identified and accessed.
In another aspect of the invention, the request itself is translated. A predetermined range of addresses are associated with an input/output (I/O) space for communicating with peripheral devices. When accessing this I/O space, the commands used are different than commands used for accessing other address spaces on the system. In order to maintain the appearance of a single-node environment, an operating system may request access to all memory locations using the same set of commands. But when accessing the I/O space, the commands are translated to appropriate commands needed for the I/O space in conformance with the multinode environment.
The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description of a preferred embodiment which proceeds with reference to the following drawings.
REFERENCES:
patent: 5117350 (1992-05-01), Parrish et al.
patent: 5303362 (1994-04-01), Butts, Jr. et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5475858 (1995-12-01), Gupta et al.
patent: 5592625 (1997-01-01), Sandberg
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5778429 (1998-07-01), Sukegawa et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 5784706 (1998-07-01), Oberlin et al.
patent: 5802578 (1998-09-01), Lovett
patent: 5860146 (1999-01-01), Vishin et al.
patent: 5897657 (1999-04-01), Hagersten et al.
patent: 5918229 (1999-06-01), Davis et al.
patent: 5933857 (1999-08-01), Br
patent: 5938765 (1999-08-01), Dove et al.
patent: 5987506 (1999-11-01), Carter et al.
patent: 6055617 (2000-04-01)
DeSota Donald R.
Dove Kenneth Frank
Gilbert Bruce M.
Lovett Thomas D.
Safranek Robert J.
Bataille Pierre-Michel
International Business Machines - Corporation
Kim Matthew
Klarquist Sparkman Campbell Leigh and Whinston LLP
LandOfFree
Multiprocessor computer system with memory map translation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiprocessor computer system with memory map translation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor computer system with memory map translation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2482182