Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-02-07
1999-10-05
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711 3, 711118, 711121, 711154, G06F 1200, G06F 1300
Patent
active
059639733
ABSTRACT:
A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.
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Baryla Robert J.
Inoshita Minoru
Shelly William A.
Vanhove Elisabeth
Bull HN Information Systems Inc.
Phillips JH H.
Solakian JS S.
Swann Tod R.
Thai Tuan V.
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