Multiprocessor communication using reduced addressing lines

Details Multiprocessor communication using reduced addressing lines Multiprocessor communication using reduced addressing lines

1999-02-15

2000-11-28

Geckil, Mehmet B.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710129, G06F 1300

Patent

active

061548049

ABSTRACT:
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

REFERENCES:
patent: 4326249 (1982-04-01), Godsey
patent: 4365294 (1982-12-01), Stokken
patent: 4365295 (1982-12-01), Katzman et al.
patent: 4454591 (1984-06-01), Lou
patent: 4535403 (1985-08-01), Holland
patent: 4675840 (1987-06-01), Raymond et al.
patent: 4716526 (1987-12-01), Mori et al.
patent: 4789852 (1988-12-01), Bailey et al.
patent: 4809164 (1989-02-01), Fuller
patent: 4837677 (1989-06-01), Burrus, Jr. et al.
patent: 4858038 (1989-08-01), Kazama
patent: 4860004 (1989-08-01), Davis
patent: 4866664 (1989-09-01), Burkhardt, Jr. et al.
patent: 4870566 (1989-09-01), Cooper et al.
patent: 4882702 (1989-11-01), Struger et al.
patent: 4970679 (1990-11-01), Tachibana
patent: 5001625 (1991-03-01), Thomas et al.
patent: 5038276 (1991-08-01), Bozzetti et al.
patent: 5060139 (1991-10-01), Theus
patent: 5119292 (1992-06-01), Baker et al.
patent: 5201055 (1993-04-01), Izquierdo et al.
patent: 5884054 (1999-03-01), Izquierdo et al.
"IBM Technical Disclosure Bulletin," vol. 31, No. 11, Apr. 1989, New York, NY, pp. 294-296.

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