Multiprocessor cache coherence directed by combined local and gl

Details Multiprocessor cache coherence directed by combined local and gl Multiprocessor cache coherence directed by combined local and gl

1996-10-01

2000-07-11

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711146, 711144, 711124, G06F 1200

Patent

active

060887699

ABSTRACT:
A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.

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