Multiprocessor arrangement including bus arbitration scheme invo

Details Multiprocessor arrangement including bus arbitration scheme invo Multiprocessor arrangement including bus arbitration scheme invo

1997-07-09

1999-08-10

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710100, 710101, 710107, 710113, 710114, 712 11, 712 15, 712 16, 712 1, 712 3, 36471601, 711157, G06F 1314

Patent

active

059352302

ABSTRACT:
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID number, not associated with a CPU in the same cluster, is associated with the opposite CPU cluster that appears to the original cluster as a "phantom" processor. A round-robin bus arbitration scheme allows ordered ownership of a common bus within a first cluster until the ID reaches the "phantom" processor, at which time bus ownership passes to a CPU in the second cluster. This arrangement is preferably symmetric, so that when a CPU from the first cluster requests ownership of the bus, it is granted bus ownership by virtue of the first cluster's appearance to the second cluster as a "phantom" CPU.

REFERENCES:
patent: 5515516 (1996-05-01), Fisch et al.
patent: 5561784 (1996-10-01), Chen et al.
patent: 5596727 (1997-01-01), Literati et al.
Pentium.RTM. Pro Family Developer's Manual, vol. 1 (Specifications), Chapter 4 (Bus Protocol), Intel.RTM. Corporation, P.O. Box 7641, Mt. Prospect, IL, 60056-7641 (order No. 242690), Jan. 1996.
IBM Technical Disclosure Bulletin vol. 32 No. 8b; Movable bus arbiter and shared bus address, Jan. 1990.
B. J. Holman (IBM Tech. Discl. Bulletin; vol. 21 No. 11; Control to enable one of duplicate circuits, Apr. 1979.

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