Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1996-07-01
1999-01-12
Barry, Lance Leonard
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711152, 711141, H01J 1300
Patent
active
058601597
ABSTRACT:
A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing of read-to-own (RTO) transaction requests over the servicing of certain read-to-share (RTS) transaction requests, even if the RTO transaction requests are received by the processing node after receipt of the RTS transaction requests. In one implementation, this is accomplished by providing a first queue within the home agent for receiving RTO transaction requests conveyed via the interconnect network which is separate from a second queue for receiving RTS transaction requests. The queues may each be implemented with FIFO buffers. A home agent control unit is configured to service a pending RTO transaction request within the RTO queue before servicing an RTS transaction request in the second queue, even though the RTS transaction request was received by the processing node from the interconnect network prior to receiving the RTO transaction request.
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Barry Lance Leonard
Kivlin B. Noel
Patru Daniel
Sun Microsystems Inc.
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