Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-01
1999-09-07
Asta, Frank J.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 711150, 711152, G06F 1300
Patent
active
059502266
ABSTRACT:
A multiprocessing computer system employing a three-hop communications protocol. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node to the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.
REFERENCES:
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5664151 (1997-09-01), Galles et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 5822763 (1998-10-01), Baylor et al.
Hagersten Erik E.
Loewenstein Paul N.
Asta Frank J.
Kivlin B. Noel
Patru Daniel
Sun Microsystems Inc.
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