Multiprocessing system employing a coherency protocol including

Details Multiprocessing system employing a coherency protocol including Multiprocessing system employing a coherency protocol including

1996-07-01

1999-04-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711148, G06F 1208

Patent

active

058976574

ABSTRACT:
A multiprocessing computer system employing a three-hop communications protocol including a reply count communication. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.

REFERENCES:
patent: 5652911 (1997-07-01), Van Venrooy et al.
Agarwala A. et al., "Experimenting With A Shared Virtual Memory Environment For Hypercubes", Journal of Parallel and Distributed Computing, vol. 29, No. 2, Sep. 1995, pp. 228-235.
Kuskin, J. et al., "The Stanford Flash Multiprocessor", Computer Architecture News, vol. 22, No. 2, Apr. 1994, pp. 302-313.
"Semi-Dynamic Distributed Data Managing Table for Distributed Shared Memory", IBM Technical Disclosure Bulletin, vol. 37, No. 5, May 1994, pp. 281-283.

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